Patents by Inventor Mark Helm

Mark Helm has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Threshold voltage distribution determination by sensing common source line currents
    Patent number: 10115457
    Abstract: Apparatuses and methods for threshold voltage (Vt) distribution determination are described. A number of apparatuses can include sense circuitry configured to determine a first current on a source line of an array of memory cells, the first current corresponding to a first quantity of memory cells of a group of memory cells that conducts in response to a first sensing voltage applied to an access line and determine a second current on the source line, the second current corresponding to a second quantity of memory cells of the group that conducts in response to a second sensing voltage applied to the access line. The number of apparatuses can include a controller configured to determine at least a portion of a Vt distribution corresponding to the group of memory cells based, at least in part, on the first current and the second current.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: October 30, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Qiang Tang, Feng Pan, Ramin Ghodsi, Mark A. Helm
  • BOOSTED CHANNEL PROGRAMMING OF MEMORY
    Publication number: 20180308551
    Abstract: Methods of operating a memory include boosting a channel voltage of a memory cell selected for programming to a particular voltage level for a particular programming pulse, boosting the channel voltage of the memory cell selected for programming to a second voltage level, greater than the particular voltage level, for a subsequent programming pulse, and boosting the channel voltage of the memory cell selected for programming to a third voltage level, greater than the second voltage level, for a next subsequent programming pulse.
    Type: Application
    Filed: March 22, 2018
    Publication date: October 25, 2018
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Mark A. Helm, Kalyan C. Kavalipurapu
  • Apparatus, systems, and methods to operate a memory
    Patent number: 10090053
    Abstract: Various embodiments, disclosed herein, include apparatus and methods to read a logic level in a selected memory cell in a selected string of a memory by sensing the logic level in response to a read current flowing through the selected string to a data line. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: October 2, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Koji Sakui, Takehiro Hasegawa, Mark Helm
  • METHOD AND APPARATUS FOR SHIELDED READ TO REDUCE PARASITIC CAPACITIVE COUPLING
    Publication number: 20180261292
    Abstract: In one embodiment, an apparatus comprises a NAND flash memory device comprising a memory device controller and a memory NAND flash memory array, the NAND flash memory device to program data into a plurality of NAND flash memory cells coupled to a wordline in a single program sequence, wherein the plurality of NAND flash memory cells are coupled to a first plurality of bitlines and a second plurality of bitlines; couple the first plurality of bitlines to a fixed bias voltage in response to a first read command; apply a read voltage to the wordline coupled to the plurality of NAND flash memory cells; and sense, via the second plurality of bitlines, data stored in NAND flash memory cells coupled to the wordline, wherein at least some bitlines of the second plurality of bitlines are each in between and directly adjacent to two respective bitlines coupled to the fixed bias voltage.
    Type: Application
    Filed: March 7, 2017
    Publication date: September 13, 2018
    Applicant: Intel Corporation
    Inventors: Mark Helm, Aaron Yip
  • APPARATUS, SYSTEMS, AND METHODS TO OPERATE A MEMORY
    Publication number: 20180233200
    Abstract: Various embodiments, disclosed herein, include apparatus and methods to read a logic level in a selected memory cell in a selected string of a memory by sensing the logic level in response to a read current flowing through the selected string to a data line. Additional apparatus, systems, and methods are disclosed.
    Type: Application
    Filed: April 16, 2018
    Publication date: August 16, 2018
    Inventors: Koji Sakui, Takehiro Hasegawa, Mark Helm
  • Three dimensional storage cell array with highly dense and scalable word line design approach
    Patent number: 10043751
    Abstract: An apparatus is described. The apparatus includes a three dimensional storage cell array structure. The apparatus also includes a staircase structure having alternating conductive and dielectric layers, wherein respective word lines are formed in the conductive layers. The word lines are connected to respective storage cells within the three dimensional storage cell array structure. The apparatus also includes upper word lines above the staircase structure that are connected to first vias that connect to respective steps of the staircase structure. The upper word lines are also connected to second vias that run vertically off a side of the staircase structure other than a side opposite the three dimensional storage cell array structure. The second vias are connected to respective word line driver transistors that are disposed beneath the staircase structure.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: August 7, 2018
    Assignee: Intel Corporation
    Inventors: Deepak Thimmegowda, Aaron Yip, Mark Helm, Yongna Li
  • Methods and apparatus having multiple select gates of different ranges of threshold voltages connected in series with memory cells
    Patent number: 10014061
    Abstract: Apparatus having a plurality of strings of series-connected memory cells, and methods of their operation, where each of the strings of series-connected memory cells is selectively connected to the same data line through a respective plurality of select gates connected in series between that string and the data line. One select gate of each of the pluralities of select gates has a threshold voltage within a first range of threshold voltages, and each remaining select gate of each of the pluralities of select gates has a threshold voltage within a second range of threshold voltages mutually exclusive from the first range of threshold voltages. Each of the select gates having a threshold voltage within the first range of threshold voltages has its control gate isolated from any of the other select gates having a threshold voltage within the first range of threshold voltages.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: July 3, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Aaron S. Yip, Mark A. Helm
  • Apparatus, systems, and methods to operate a memory
    Patent number: 9972391
    Abstract: Various embodiments, disclosed herein, include apparatus and methods to read a logic level in a selected memory cell in a selected string of a memory by sensing the logic level in response to a read current flowing through the selected string to a data line. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: May 15, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Koji Sakui, Takehiro Hasegawa, Mark Helm
  • Boosted channel programming of memory
    Patent number: 9947418
    Abstract: Methods of operating a memory include generating a programming pulse for a programming operation having a plurality of steps prior to a program voltage level of the programming pulse, and generating a subsequent programming pulse for the programming operation having the plurality of steps prior to a program voltage level of the subsequent programming pulse, wherein a particular step of the plurality of steps of the programming pulse has a different magnitude than a corresponding step of the plurality of steps of the subsequent programming pulse.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: April 17, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Mark A. Helm, Kalyan C. Kavalipurapu
  • APPARATUSES AND METHODS FOR GENERATING PROBABILISTIC INFORMATION WITH CURRENT INTEGRATION SENSING
    Publication number: 20180081753
    Abstract: Methods and apparatuses for generating probabilistic information for error correction using current integration are disclosed. An example method comprises sensing a first plurality of memory cells based on a first sense threshold, responsive to sensing the first plurality of cells, associating a first set of probabilistic information with the first plurality of memory cells, sensing a second plurality of memory cells based on a second sense threshold, responsive to sensing the second plurality of memory cells, associating a second set of probabilistic information with the second plurality of memory cells, and performing an error correction operation on the first and second pluralities of memory cells based, at least in part, on the first and second values.
    Type: Application
    Filed: September 16, 2016
    Publication date: March 22, 2018
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Patrick R. Khayat, Sivagnanam Parthasarathy, Mustafa N. Kaynak, Mark A. Helm, Aaron S. Yip
  • BOOSTED CHANNEL PROGRAMMING OF MEMORY
    Publication number: 20170294233
    Abstract: Methods of operating a memory include generating a programming pulse for a programming operation having a plurality of steps prior to a program voltage level of the programming pulse, and generating a subsequent programming pulse for the programming operation having the plurality of steps prior to a program voltage level of the subsequent programming pulse, wherein a particular step of the plurality of steps of the programming pulse has a different magnitude than a corresponding step of the plurality of steps of the subsequent programming pulse.
    Type: Application
    Filed: April 12, 2016
    Publication date: October 12, 2017
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Mark A. Helm, Kalyan C. Kavalipurapu
  • THREE DIMENSIONAL STORAGE CELL ARRAY WITH HIGHLY DENSE AND SCALABLE WORD LINE DESIGN APPROACH
    Publication number: 20170287833
    Abstract: An apparatus is described. The apparatus includes a three dimensional storage cell array structure. The apparatus also includes a staircase structure having alternating conductive and dielectric layers, wherein respective word lines are formed in the conductive layers. The word lines are connected to respective storage cells within the three dimensional storage cell array structure. The apparatus also includes upper word lines above the staircase structure that are connected to first vias that connect to respective steps of the staircase structure. The upper word lines are also connected to second vias that run vertically off a side of the staircase structure other than a side opposite the three dimensional storage cell array structure. The second vias are connected to respective word line driver transistors that are disposed beneath the staircase structure.
    Type: Application
    Filed: March 30, 2016
    Publication date: October 5, 2017
    Inventors: Deepak THIMMEGOWDA, Aaron YIP, Mark HELM, Yongna LI
  • Method and system to obtain state confidence data using multistrobe read of a non-volatile memory
    Patent number: 9754683
    Abstract: An apparatus may include a processor circuit a processor circuit to retrieve data from a non-volatile memory, and a multistrobe read module operable on the processor circuit to set a read operation to read a memory cell over a multiplicity of sense operations, where each sense operation is performed under a different sense condition. The multistrobe read module may be further operable to schedule a new sense operation to succeed a prior sense operation of the multiplicity of sense operations without recharge of the wordline when a value of one or more read condition is within a preset range. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: September 5, 2017
    Assignee: INTEL CORPORATION
    Inventors: Matthew Goldman, Krishna K. Parat, Pranav Kalavade, Nathan R. Franklin, Mark Helm
  • THRESHOLD VOLTAGE DISTRIBUTION DETERMINATION
    Publication number: 20170169885
    Abstract: Apparatuses and methods for threshold voltage (Vt) distribution determination are described. A number of apparatuses can include sense circuitry configured to determine a first current on a source line of an array of memory cells, the first current corresponding to a first quantity of memory cells of a group of memory cells that conducts in response to a first sensing voltage applied to an access line and determine a second current on the source line, the second current corresponding to a second quantity of memory cells of the group that conducts in response to a second sensing voltage applied to the access line. The number of apparatuses can include a controller configured to determine at least a portion of a Vt distribution corresponding to the group of memory cells based, at least in part, on the first current and the second current.
    Type: Application
    Filed: February 28, 2017
    Publication date: June 15, 2017
    Inventors: Qiang Tang, Feng Pan, Ramin Ghodsi, Mark A. Helm
  • Three dimensional memory control circuitry
    Patent number: 9620229
    Abstract: An integrated circuit includes a memory array, a wordline circuit, divided into at least two subcircuits, to control the memory array, and a bitline circuit, divided into at least two subcircuits, to control the memory array. The wordline subcircuits and the bitline subcircuits at least partially overlap separate respective regions of the memory array.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: April 11, 2017
    Assignee: Intel Corporation
    Inventors: Mark Helm, Jung Sheng Hoei, Aaron Yip, Dzung Nguyen
  • Threshold voltage distribution determination
    Patent number: 9607692
    Abstract: Apparatuses and methods for threshold voltage (Vt) distribution determination are described. A number of apparatuses can include sense circuitry configured to determine a first current on a source line of an array of memory cells, the first current corresponding to a first quantity of memory cells of a group of memory cells that conducts in response to a first sensing voltage applied to an access line and determine a second current on the source line, the second current corresponding to a second quantity of memory cells of the group that conducts in response to a second sensing voltage applied to the access line. The number of apparatuses can include a controller configured to determine at least a portion of a Vt distribution corresponding to the group of memory cells based, at least in part, on the first current and the second current.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: March 28, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Qiang Tang, Feng Pan, Ramin Ghodsi, Mark A. Helm
  • SENSE OPERATION FLAGS IN A MEMORY DEVICE
    Publication number: 20170075613
    Abstract: In a memory device, odd bit lines of a flag memory cell array are connected with a short circuit to a dynamic data cache. Even bit lines of the flag memory cell array are disconnected from the dynamic data cache. When an even page of a main memory cell array is read, the odd flag memory cells, comprising flag data, are read at the same time so that it can be determined whether the odd page of the main memory cell array has been programmed. If the flag data indicates that the odd page has not been programmed, threshold voltage windows can be adjusted to determine the states of the sensed even memory cell page.
    Type: Application
    Filed: November 3, 2016
    Publication date: March 16, 2017
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Shafqat Ahmed, Khaled Hasnat, Pranav Kalavade, Krishna Parat, Aaron Yip, Mark A. Helm, Andrew Bicksler
  • Memory cell sensing
    Patent number: 9576674
    Abstract: This disclosure concerns memory cell sensing. One or more methods include determining a data state of a first memory cell coupled to a first data line, determining a data state of a third memory cell coupled to a third data line, transferring determined data of at least one of the first and the third memory cells to a data line control unit corresponding to a second data line to which a second memory cell is coupled, the second data line being adjacent to the first data line and the third data line, and determining a data state of the second memory cell based, at least partially, on the transferred determined data.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: February 21, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Matthew Goldman, Pranav Kalavade, Uday Chandrasekhar, Mark A. Helm
  • Methods, devices, and systems for data sensing
    Patent number: 9552888
    Abstract: Methods and devices for data sensing are disclosed. One such method includes performing a number of successive sense operations on a number of memory cells using a number of different sensing voltages, determining a quantity of the number memory cells that change states between consecutive sense operations of the number of successive sense operations, and determining, based at least partially on the determined quantity of the number of memory cells that change states between consecutive sense operations, whether to output hard data corresponding to one of the number of successive sense operations.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: January 24, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Mark A. Helm, Uday Chandrasekhar
  • Sense operation flags in a memory device
    Patent number: 9519582
    Abstract: Memory devices, methods for programming sense flags, methods for sensing flags, and memory systems are disclosed. In one such memory device, the odd bit lines of a flag memory cell array are connected with a short circuit to a dynamic data cache. The even bit lines of the flag memory cell array are disconnected from the dynamic data cache. When an even page of a main memory cell array is read, the odd flag memory cells, comprising flag data, are read at the same time so that it can be determined whether the odd page of the main memory cell array has been programmed. If the flag data indicates that the odd page has not been programmed, threshold voltage windows can be adjusted to determine the states of the sensed even memory cell page.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: December 13, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Shafqat Ahmed, Khaled Hasnat, Pranav Kalavade, Krishna Parat, Aaron Yip, Mark A. Helm, Andrew Bicksler