Patents by Inventor Mark Helm

Mark Helm has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Data line arrangement and pillar arrangement in apparatuses
    Patent number: 9431421
    Abstract: Some embodiments include an apparatus having semiconductor pillars in a substantially hexagonally closest packed arrangement. The hexagonally closest packed arrangement includes a repeating pillar pattern which has at least portions of 7 different pillars. Each of the different pillars in a respective one of the repeating pillar patterns is capable of being electrically coupled to a different data line of a plurality of data lines. Some embodiments include an apparatus having semiconductor pillars in a substantially hexagonally closest packed arrangement. The hexagonally closest packed arrangement includes a repeating pillar pattern having at least portions of 7 different pillars. All 7 different pillars of a repeating pillar pattern are encompassed by a single drain-side select gate (SGD).
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: August 30, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Luyen Vu, Mark A. Helm
  • THREE DIMENSIONAL MEMORY CONTROL CIRCUITRY
    Publication number: 20160196879
    Abstract: An integrated circuit includes a memory array, a wordline circuit, divided into at least two subcircuits, to control the memory array, and a bitline circuit, divided into at least two subcircuits, to control the memory array. The wordline subcircuits and the bitline subcircuits at least partially overlap separate respective regions of the memory array.
    Type: Application
    Filed: October 29, 2015
    Publication date: July 7, 2016
    Inventors: MARK HELM, JUNG SHENG HOEI, AARON YIP, DZUNG NGUYEN
  • APPARATUS, SYSTEMS, AND METHODS TO OPERATE A MEMORY
    Publication number: 20160180934
    Abstract: Various embodiments, disclosed herein, include apparatus and methods to read a logic level in a selected memory cell in a selected string of a memory by sensing the logic level in response to a read current flowing through the selected string to a data line. Additional apparatus, systems, and methods are disclosed.
    Type: Application
    Filed: December 16, 2015
    Publication date: June 23, 2016
    Inventors: Koji Sakui, Takehiro Hasegawa, Mark Helm
  • Memory program disturb reduction
    Patent number: 9330777
    Abstract: Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method can include applying, during a first pass of programming, a first bias voltage value to a source select gate to isolate memory cells from a source, applying a programming voltage to an access line of a page of the memory cells during the first pass of programming, and applying a second bias voltage value to the source select gate to isolate the memory cells from the source during a second pass of programming. Further devices, systems, and methods are disclosed.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: May 3, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Akira Goda, Mark Helm, Pranav Kalavade, Charan Srinivasan
  • THRESHOLD VOLTAGE DISTRIBUTION DETERMINATION
    Publication number: 20160099048
    Abstract: Apparatuses and methods for threshold voltage (Vt) distribution determination are described. A number of apparatuses can include sense circuitry configured to determine a first current on a source line of an array of memory cells, the first current corresponding to a first quantity of memory cells of a group of memory cells that conducts in response to a first sensing voltage applied to an access line and determine a second current on the source line, the second current corresponding to a second quantity of memory cells of the group that conducts in response to a second sensing voltage applied to the access line. The number of apparatuses can include a controller configured to determine at least a portion of a Vt distribution corresponding to the group of memory cells based, at least in part, on the first current and the second current.
    Type: Application
    Filed: September 29, 2015
    Publication date: April 7, 2016
    Inventors: Qiang Tang, Feng Pan, Ramin Ghodsi, Mark A. Helm
  • Memory kink checking
    Patent number: 9251908
    Abstract: This disclosure concerns memory kink checking. One embodiment includes selectively applying one of a plurality of voltages to a first data line according to a programming status of a first memory cell, wherein the first memory cell is coupled to the first data line and to a selected access line. An effect on a second data line is determined, due at least in part to the voltage applied to the first data line and a capacitive coupling between at least the first data line and the second data line, wherein the second data line is coupled to a second memory cell, the second memory cell is adjacent to the first memory cell, and the second memory cell is coupled to the selected access line. A kink correction is applied to the second data line, responsive to the determined effect, during a subsequent programming pulse applied to the second memory cell.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: February 2, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Uday Chandrasekhar, Mark A. Helm
  • Memory devices with local and global devices at substantially the same level above stacked tiers of memory cells and methods
    Patent number: 9251860
    Abstract: In an embodiment, a memory device includes a stack of tiers of memory cells, a tier of local devices at a level above the stack of tiers of memory cells, and a tier of global devices at substantially a same level as the tier of local devices. A local device may provide selective access to a data line. A global device may provide selective access to a global access line. A tier of memory cells may be selectively coupled to a global access line by the global device of the tier of global devices.
    Type: Grant
    Filed: June 10, 2015
    Date of Patent: February 2, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Aaron S. Yip, Mark A. Helm, Ramin Ghodsi
  • Data Line Arrangement and Pillar Arrangement in Apparatuses
    Publication number: 20160005761
    Abstract: Some embodiments include an apparatus having semiconductor pillars in a substantially hexagonally closest packed arrangement. The hexagonally closest packed arrangement includes a repeating pillar pattern which has at least portions of 7 different pillars. Each of the different pillars in a respective one of the repeating pillar patterns is capable of being electrically coupled to a different data line of a plurality of data lines. Some embodiments include an apparatus having semiconductor pillars in a substantially hexagonally closest packed arrangement. The hexagonally closest packed arrangement includes a repeating pillar pattern having at least portions of 7 different pillars. All 7 different pillars of a repeating pillar pattern are encompassed by a single drain-side select gate (SGD).
    Type: Application
    Filed: September 10, 2015
    Publication date: January 7, 2016
    Inventors: Luyen Vu, Mark A. Helm
  • SENSE OPERATION FLAGS IN A MEMORY DEVICE
    Publication number: 20150363313
    Abstract: Memory devices, methods for programming sense flags, methods for sensing flags, and memory systems are disclosed. In one such memory device, the odd bit lines of a flag memory cell array are connected with a short circuit to a dynamic data cache. The even bit lines of the flag memory cell array are disconnected from the dynamic data cache. When an even page of a main memory cell array is read, the odd flag memory cells, comprising flag data, are read at the same time so that it can be determined whether the odd page of the main memory cell array has been programmed. If the flag data indicates that the odd page has not been programmed, threshold voltage windows can be adjusted to determine the states of the sensed even memory cell page.
    Type: Application
    Filed: August 24, 2015
    Publication date: December 17, 2015
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Shafqat Ahmed, Khaled Hasnat, Pranav Kalavade, Krishna Parat, Aaron Yip, Mark A. Helm, Andrew Bicksler
  • Three dimensional memory control circuitry
    Patent number: 9202536
    Abstract: An integrated circuit includes a memory array, a wordline circuit, divided into at least two subcircuits, to control the memory array, and a bitline circuit, divided into at least two subcircuits, to control the memory array. The wordline subcircuits and the bitline subcircuits at least partially overlap separate respective regions of the memory array.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: December 1, 2015
    Assignee: Intel Corporation
    Inventors: Mark Helm, Jung Sheng Hoei, Aaron Yip, Dzung Nguyen
  • Data line arrangement and pillar arrangement in apparatuses
    Patent number: 9159736
    Abstract: Some embodiments include an apparatus having semiconductor pillars in a substantially hexagonally closest packed arrangement. The hexagonally closest packed arrangement includes a repeating pillar pattern which has at least portions of 7 different pillars. Each of the different pillars in a respective one of the repeating pillar patterns is capable of being electrically coupled to a different data line of a plurality of data lines. Some embodiments include an apparatus having semiconductor pillars in a substantially hexagonally closest packed arrangement. The hexagonally closest packed arrangement includes a repeating pillar pattern having at least portions of 7 different pillars. All 7 different pillars of a repeating pillar pattern are encompassed by a single drain-side select gate (SGD).
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: October 13, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Luyen Vu, Mark A. Helm
  • MEMORY DEVICES WITH LOCAL AND GLOBAL DEVICES AT SUBSTANTIALLY THE SAME LEVEL ABOVE STACKED TIERS OF MEMORY CELLS AND METHODS
    Publication number: 20150279432
    Abstract: In an embodiment, a memory device includes a stack of tiers of memory cells, a tier of local devices at a level above the stack of tiers of memory cells, and a tier of global devices at substantially a same level as the tier of local devices. A local device may provide selective access to a data line. A global device may provide selective access to a global access line. A tier of memory cells may be selectively coupled to a global access line by the global device of the tier of global devices.
    Type: Application
    Filed: June 10, 2015
    Publication date: October 1, 2015
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Aaron S. Yip, Mark A. Helm, Ramin Ghodsi
  • METHODS, DEVICES, AND SYSTEMS FOR DATA SENSING
    Publication number: 20150262695
    Abstract: The present disclosure includes methods and devices for data sensing. One such method includes performing a number of successive sense operations on a number of memory cells using a number of different sensing voltages, determining a quantity of the number memory cells that change states between consecutive sense operations of the number of successive sense operations, and determining, based at least partially on the determined quantity of the number of memory cells that change states between consecutive sense operations, whether to output hard data corresponding to one of the number of successive sense operations.
    Type: Application
    Filed: May 28, 2015
    Publication date: September 17, 2015
    Inventors: Mark A. Helm, Uday Chandrasekhar
  • Sense operation flags in a memory device
    Patent number: 9135998
    Abstract: Memory devices, methods for programming sense flags, methods for sensing flags, and memory systems are disclosed. In one such memory device, the odd bit lines of a flag memory cell array are connected with a short circuit to a dynamic data cache. The even bit lines of the flag memory cell array are disconnected from the dynamic data cache. When an even page of a main memory cell array is read, the odd flag memory cells, comprising flag data, are read at the same time so that it can be determined whether the odd page of the main memory cell array has been programmed. If the flag data indicates that the odd page has not been programmed, threshold voltage windows can be adjusted to determine the states of the sensed even memory cell page.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: September 15, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Shafqat Ahmed, Khaled Hasnat, Pranav Kalavade, Krishna Parat, Aaron Yip, Mark A. Helm, Andrew Bicksler
  • DATA LINE ARRANGEMENT AND PILLAR ARRANGEMENT IN APPARATUSES
    Publication number: 20150228659
    Abstract: Some embodiments include an apparatus having semiconductor pillars in a substantially hexagonally closest packed arrangement. The hexagonally closest packed arrangement includes a repeating pillar pattern which has at least portions of 7 different pillars. Each of the different pillars in a respective one of the repeating pillar patterns is capable of being electrically coupled to a different data line of a plurality of data lines. Some embodiments include an apparatus having semiconductor pillars in a substantially hexagonally closest packed arrangement. The hexagonally closest packed arrangement includes a repeating pillar pattern having at least portions of 7 different pillars. All 7 different pillars of a repeating pillar pattern are encompassed by a single drain-side select gate (SGD).
    Type: Application
    Filed: February 7, 2014
    Publication date: August 13, 2015
    Applicant: Micron Technology, Inc.
    Inventors: Luyen Vu, Mark A. Helm
  • MEMORY CELL SENSING
    Publication number: 20150194218
    Abstract: This disclosure concerns memory cell sensing. One or more methods include determining a data state of a first memory cell coupled to a first data line, determining a data state of a third memory cell coupled to a third data line, transferring determined data of at least one of the first and the third memory cells to a data line control unit corresponding to a second data line to which a second memory cell is coupled, the second data line being adjacent to the first data line and the third data line, and determining a data state of the second memory cell based, at least partially, on the transferred determined data.
    Type: Application
    Filed: March 19, 2015
    Publication date: July 9, 2015
    Inventors: Matthew Goldman, Pranav Kalavade, Uday Chandrasekhar, Mark A. Helm
  • Memory devices with local and global devices at substantially the same level above stacked tiers of memory cells and methods
    Patent number: 9070442
    Abstract: In an embodiment, a memory device includes a stack of tiers of memory cells, a tier of local devices at a level above the stack of tiers of memory cells, and a tier of global devices at substantially a same level as the tier of local devices. A local device may provide selective access to a data line. A global device may provide selective access to a global access line. A tier of memory cells may be selectively coupled to a global access line by the global device of the tier of global devices.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: June 30, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Aaron S. Yip, Mark A. Helm, Ramin Ghodsi
  • MEMORY PROGRAM DISTURB REDUCTION
    Publication number: 20150170756
    Abstract: Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method can include applying, during a first pass of programming, a first bias voltage value to a source select gate to isolate memory cells from a source, applying a programming voltage to an access line of a page of the memory cells during the first pass of programming, and applying a second bias voltage value to the source select gate to isolate the memory cells from the source during a second pass of programming. Further devices, systems, and methods are disclosed.
    Type: Application
    Filed: February 26, 2015
    Publication date: June 18, 2015
    Inventors: Akira Goda, Mark Helm, Pranav Kalavade, Charan Srinivasan
  • Methods, devices, and systems for data sensing
    Patent number: 9047972
    Abstract: Methods, devices, and systems for data sensing in a memory system can include performing a number of successive sense operations on a number of memory cells using a number of different sensing voltages, determining a quantity of the number memory cells that change states between consecutive sense operations of the number of successive sense operations, and determining, based at least partially on the determined quantity of the number of memory cells that change states between consecutive sense operations, whether to output hard data corresponding to one of the number of successive sense operations.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: June 2, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Mark A. Helm, Uday Chandrasekhar
  • Memory cell sensing
    Patent number: 9001577
    Abstract: This disclosure concerns memory cell sensing. One or more methods include determining a data state of a first memory cell coupled to a first data line, determining a data state of a third memory cell coupled to a third data line, transferring determined data of at least one of the first and the third memory cells to a data line control unit corresponding to a second data line to which a second memory cell is coupled, the second data line being adjacent to the first data line and the third data line, and determining a data state of the second memory cell based, at least partially, on the transferred determined data.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: April 7, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Matthew Goldman, Pranav Kalavade, Uday Chandrasekhar, Mark A. Helm