Patents by Inventor Mark Horowitz
Mark Horowitz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11823757Abstract: Volatile memory devices may be on a first memory module that is coupled to a memory controller by a first signal path. A nonvolatile memory device may be on a second memory module that is coupled to the first memory module by a second signal path. A memory transaction for the nonvolatile memory device may be transferred from the memory controller to at least one of the volatile memory devices using the first signal path and data associated with the memory transaction is to be written from at least one of the volatile memory devices to the nonvolatile memory device using the second signal path and a control signal. A durability circuit may generate the control signal based on a comparison of a number of write transactions to a particular memory location with a threshold value.Type: GrantFiled: August 21, 2020Date of Patent: November 21, 2023Assignee: Rambus Inc.Inventors: Craig Hampel, Mark Horowitz
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Publication number: 20210035652Abstract: Volatile memory devices may be on a first memory module that is coupled to a memory controller by a first signal path. A nonvolatile memory device may be on a second memory module that is coupled to the first memory module by a second signal path. A memory transaction for the nonvolatile memory device may be transferred from the memory controller to at least one of the volatile memory devices using the first signal path and data associated with the memory transaction is to be written from at least one of the volatile memory devices to the nonvolatile memory device using the second signal path and a control signal. A durability circuit may generate the control signal based on a comparison of a number of write transactions to a particular memory location with a threshold value.Type: ApplicationFiled: August 21, 2020Publication date: February 4, 2021Inventors: Craig Hampel, Mark Horowitz
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Patent number: 10755794Abstract: Volatile memory devices may be on a first memory module that is coupled to a memory controller by a first signal path. A nonvolatile memory device may be on a second memory module that is coupled to the first memory module by a second signal path. A memory transaction for the nonvolatile memory device may be transferred from the memory controller to at least one of the volatile memory devices using the first signal path and data associated with the memory transaction is to be written from at least one of the volatile memory devices to the nonvolatile memory device using the second signal path and a control signal. A durability circuit may generate the control signal based on a comparison of a number of write transactions to a particular memory location with a threshold value.Type: GrantFiled: August 30, 2017Date of Patent: August 25, 2020Assignee: Rambus Inc.Inventors: Craig Hampel, Mark Horowitz
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Publication number: 20170365354Abstract: Volatile memory devices may be on a first memory module that is coupled to a memory controller by a first signal path. A nonvolatile memory device may be on a second memory module that is coupled to the first memory module by a second signal path. A memory transaction for the nonvolatile memory device may be transferred from the memory controller to at least one of the volatile memory devices using the first signal path and data associated with the memory transaction is to be written from at least one of the volatile memory devices to the nonvolatile memory device using the second signal path and a control signal. A durability circuit may generate the control signal based on a comparison of a number of write transactions to a particular memory location with a threshold value.Type: ApplicationFiled: August 30, 2017Publication date: December 21, 2017Inventors: Craig Hampel, Mark Horowitz
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Patent number: 9767918Abstract: Volatile memory devices may be on a first memory module that is coupled to a memory controller by a first signal path. A nonvolatile memory device may be on a second memory module that is coupled to the first memory module by a second signal path. A memory transaction for the nonvolatile memory device may be transferred from the memory controller to at least one of the volatile memory devices using the first signal path and data associated with the memory transaction is to be written from at least one of the volatile memory devices to the nonvolatile memory device using the second signal path and a control signal. A defect circuit may generate the control signal in view of a detection of a defect in the nonvolatile memory device based on a comparison of a test value read from a memory location to a stored value.Type: GrantFiled: September 30, 2016Date of Patent: September 19, 2017Assignee: Rambus Inc.Inventors: Craig Hampel, Mark Horowitz
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Publication number: 20170025187Abstract: Volatile memory devices may be on a first memory module that is coupled to a memory controller by a first signal path. A nonvolatile memory device may be on a second memory module that is coupled to the first memory module by a second signal path. A memory transaction for the nonvolatile memory device may be transferred from the memory controller to at least one of the volatile memory devices using the first signal path and data associated with the memory transaction is to be written from at least one of the volatile memory devices to the nonvolatile memory device using the second signal path and a control signal. A defect circuit may generate the control signal in view of a detection of a defect in the nonvolatile memory device based on a comparison of a test value read from a memory location to a stored value.Type: ApplicationFiled: September 30, 2016Publication date: January 26, 2017Inventors: Craig Hampel, Mark Horowitz
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Patent number: 9460021Abstract: Volatile memory devices corresponding to a first memory hierarchy may be on a first memory module that is coupled to a memory controller by a first signal path. A nonvolatile memory device corresponding to a second memory hierarchy may be on a second memory module that is coupled to the first memory module by a second signal path. Memory transactions for the nonvolatile memory device may be transferred from the memory controller to the first memory hierarchy using the first signal path, and data associated with an accumulation of the memory transactions may be written from the first memory hierarchy to the second memory hierarchy using the second signal path and a first and second control signal. The first control signal may be generated in view of a detection of wear and the second control signal may be generated in view of a detection of a defect.Type: GrantFiled: October 15, 2015Date of Patent: October 4, 2016Assignee: Rambus Inc.Inventors: Craig Hampel, Mark Horowitz
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Publication number: 20160098354Abstract: Volatile memory devices corresponding to a first memory hierarchy may be on a first memory module that is coupled to a memory controller by a first signal path. A nonvolatile memory device corresponding to a second memory hierarchy may be on a second memory module that is coupled to the first memory module by a second signal path. Memory transactions for the nonvolatile memory device may be transferred from the memory controller to the first memory hierarchy using the first signal path, and data associated with an accumulation of the memory transactions may be written from the first memory hierarchy to the second memory hierarchy using the second signal path and a first and second control signal. The first control signal may be generated in view of a detection of wear and the second control signal may be generated in view of a detection of a defect.Type: ApplicationFiled: October 15, 2015Publication date: April 7, 2016Inventors: Craig Hampel, Mark Horowitz
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Patent number: 9195602Abstract: A memory system is disclosed comprising a memory controller and a first set of volatile memory devices defining a first memory hierarchy. The first set of volatile memory devices are disposed on at least one first memory module, which is coupled to the memory controller in a daisy-chained configuration. A first integrated circuit buffer device is included on the module. The system has a second set of nonvolatile memory devices defining a second memory hierarchy. The second set of nonvolatile memory devices are disposed on at least one second memory module, which is coupled to the at least one first memory module in a daisy-chained configuration. The second module includes a second integrated circuit buffer device. The system is configured such that signals transmitted between the memory controller and the second memory hierarchy pass through the first memory hierarchy.Type: GrantFiled: March 19, 2008Date of Patent: November 24, 2015Assignee: Rambus Inc.Inventors: Craig Hampel, Mark Horowitz
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Patent number: 8966413Abstract: A chip generator according to an embodiment of the present invention codifies designer knowledge and design trade-offs into a template that can be used to create many different chips. Like reconfigurable designs, an embodiment of the present invention fixes the top level system architecture, amortizes software and validation and design costs, and enables a rich system simulation environment for application developers. Meanwhile, below the top level, the developer can “program” the individual inner components of the architecture. Unlike reconfigurable chips, a chip generator according to an embodiment of the present invention, compiles the program to create a customized chip. This compilation process occurs at elaboration time—long before silicon is fabricated. The result is a framework that enables more customization of the generated chip at the architectural level because additional components and logic can be added if the customization process requires it.Type: GrantFiled: February 17, 2012Date of Patent: February 24, 2015Assignee: The Board of Trustees of the Leland Stanford Junior UniversityInventors: Ofer Shacham, Mark Horowitz, Stephen Richardson
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Patent number: 8892619Abstract: A floating-point fused multiply-add (FMA) unit embodied in an integrated circuit includes a multiplier circuit cascaded with an adder circuit to produce a result A*C+B. To decrease latency, the FMA includes accumulation bypass circuits forwarding an unrounded result of the adder to inputs of the close path and the far path circuits of the adder, and forwarding an exponent result in carry save format to an input of the exponent difference circuit. Also included in the FMA is a multiply-add bypass circuit forwarding the unrounded result to the inputs of the multiplier circuit. The adder circuit includes an exponent difference circuit implemented in parallel with the multiplier circuit; a close path circuit implemented after the exponent difference circuit; and a far path circuit implemented after the exponent difference circuit.Type: GrantFiled: July 24, 2012Date of Patent: November 18, 2014Assignee: The Board of Trustees of the Leland Stanford Junior UniversityInventors: Sameh Galal, Mark Horowitz
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Publication number: 20140188966Abstract: A floating-point fused multiply-add (FMA) unit embodied in an integrated circuit includes a multiplier circuit cascaded with an adder circuit to produce a result A*C+B. To decrease latency, the FMA includes accumulation bypass circuits forwarding an unrounded result of the adder to inputs of the close path and the far path circuits of the adder, and forwarding an exponent result in carry save format to an input of the exponent difference circuit. Also included in the FMA is a multiply-add bypass circuit forwarding the unrounded result to the inputs of the multiplier circuit. The adder circuit includes an exponent difference circuit implemented in parallel with the multiplier circuit; a close path circuit implemented after the exponent difference circuit; and a far path circuit implemented after the exponent difference circuit.Type: ApplicationFiled: July 24, 2012Publication date: July 3, 2014Inventors: Sameh Galal, Mark Horowitz
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Publication number: 20130068422Abstract: A system for recycling energy from ice remnants. The system includes a container. The container includes a receptacle configured to receive ice remnants. An ice capturing and melting device below the receptacle is configured to capture and melt ice in the ice remnants while allowing fluid in the ice remnants to pass therethrough thereby forming a cooled recycled liquid at a bottom of the container. A discharge port located proximate the bottom of the container is configured to direct the cooled recycled liquid to at least one heat source of a facility and cool the heat source.Type: ApplicationFiled: September 15, 2011Publication date: March 21, 2013Inventor: Alan Mark Horowitz
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Publication number: 20120324408Abstract: A chip generator according to an embodiment of the present invention codifies designer knowledge and design trade-offs into a template that can be used to create many different chips. Like reconfigurable designs, an embodiment of the present invention fixes the top level system architecture, amortizes software and validation and design costs, and enables a rich system simulation environment for application developers. Meanwhile, below the top level, the developer can “program” the individual inner components of the architecture. Unlike reconfigurable chips, a chip generator according to an embodiment of the present invention, compiles the program to create a customized chip. This compilation process occurs at elaboration time—long before silicon is fabricated. The result is a framework that enables more customization of the generated chip at the architectural level because additional components and logic can be added if the customization process requires it.Type: ApplicationFiled: February 17, 2012Publication date: December 20, 2012Applicant: The Board of Trustees of the Leland Stanford Junior UniversityInventors: Ofer Shacham, Mark Horowitz, Stephen Richardson
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Patent number: 8185853Abstract: Embodiments in the present disclosure pertain to domain translators. A domain translator converts a variable from one domain to a different domain. Domains include, but are not limited to, voltage, current, frequency, phase, delay, and duty-cycle. In particular, domain translators enable conversion between standard voltage and current domains commonly used by circuit simulators to other domains such as frequency, phase, delay, duty-cycle, etc., so that linear analysis can be performed on a wide range of circuits that exhibit linear behavior in domains other than voltage and current.Type: GrantFiled: February 28, 2008Date of Patent: May 22, 2012Assignee: Rambus Inc.Inventors: Jaeha Kim, Kevin D. Jones, Mark Horowitz
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Patent number: 8116366Abstract: Disclosed is a delayed decision feedback sequence estimator comprising a delayed decision feedback sequence estimator main unit including DDFSE computing unit group including (L+M) DDFSE computing units, equal in number to a length of each of plurality of blocks into which a received data symbol sequence is divided; wherein (L+M) DDFSE computing units are connected in a pipeline configuration to execute delayed decision feedback sequence estimation of the blocks in parallel; and an edge effect detection and correction circuit that detects an edge effect due to processing the delayed decision feedback sequence estimation of the separated block and corrects a relevant bit error.Type: GrantFiled: April 28, 2008Date of Patent: February 14, 2012Assignees: Renesas Electronics Corporation, The Board of Trustees of the Leland Stanford Junior UniversityInventors: Toshitsugu Kawashima, Mark Horowitz
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Patent number: 8027531Abstract: This invention relates to an apparatus and a method for video capture of a three-dimensional region of interest in a scene using an array of video cameras. The video cameras of the array are positioned for viewing the three-dimensional region of interest in the scene from their respective viewpoints. A triggering mechanism is provided for staggering the capture of a set of frames by the video cameras of the array. The apparatus has a processing unit for combining and operating on the set of frames captured by the array of cameras to generate a new visual output, such as high-speed video or spatio-temporal structure and motion models, that has a synthetic viewpoint of the three-dimensional region of interest. The processing involves spatio-temporal interpolation for determining the synthetic viewpoint space-time trajectory. In some embodiments, the apparatus computes a multibaseline spatio-temporal optical flow.Type: GrantFiled: July 21, 2005Date of Patent: September 27, 2011Assignee: The Board of Trustees of the Leland Stanford Junior UniversityInventors: Bennett Wilburn, Neel Joshi, Marc C. Levoy, Mark Horowitz
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Patent number: 7859436Abstract: A memory device includes a receiver to receive a first input data signal and to create an output signal corresponding to the first input data signal and a voltage representative of a second signal received earlier in time than the first input data signal. A memory system includes a memory controller and one or more memory devices, at least one or which includes a receiver to receive a first input data signal and to create an output signal corresponding to the first input data signal and a voltage representative of a second signal received earlier in time than the first input data signal.Type: GrantFiled: October 24, 2008Date of Patent: December 28, 2010Assignee: Rambus Inc.Inventors: Carl Werner, Mark Horowitz, Pak Chau, Scott Best, Stefanos Sidiropoulos
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Publication number: 20100199237Abstract: Embodiments in the present disclosure pertain to domain translators. A domain translator converts a variable from one domain to a different domain. Domains include, but are not limited to, voltage, current, frequency, phase, delay, and duty-cycle. In particular, domain translators enable conversion between standard voltage and current domains commonly used by circuit simulators to other domains such as frequency, phase, delay, duty-cycle, etc., so that linear analysis can be performed on a wide range of circuits that exhibit linear behavior in domains other than voltage and current.Type: ApplicationFiled: February 28, 2008Publication date: August 5, 2010Applicant: RAMBUS INC.Inventors: Jaeha Kim, Kevin D. Jones, Mark Horowitz
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Patent number: 7765074Abstract: A circuit, apparatus and method obtains system margin at the receive circuit using phase shifted data sampling clocks while allowing the CDR to remain synchronized with the incoming data stream in embodiments. In an embodiment, a circuit includes first and second samplers to sample a data signal and output data and edge information in response to a data clock signal and an edge clock signal. A phase detector generates phase information in response to the data information and the edge information. A clock phase adjustment circuit generates the data clock signal and the edge clock signal in response to the data information during a synchronization mode. The clock phase adjustment circuit increments a phase of the data clock signal during a waveform capture mode.Type: GrantFiled: June 2, 2006Date of Patent: July 27, 2010Assignee: Rambus Inc.Inventors: Dennis Kim, Jared Zerbe, Mark Horowitz, William Stonecypher