Abstract: A controller device for controlling a synchronous dynamic random access memory device. The controller device includes output driver circuitry to output block size information to the memory device. The block size information defines an amount of data to be output by the memory device. In addition, the controller device includes input receiver circuitry to receive the amount of data output by the memory device.

Abstract: The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention.

Abstract: An integrated circuit device that includes a clock synchronization circuit. The clock synchronization circuit receives an external clock signal and generates an internal clock signal from the external clock signal using a feedback loop. The internal clock signal is adjusted based on feedback provided via the feedback loop. In addition, the integrated circuit device includes an output circuit. The output circuit includes an output driver to output at least two bits of data in succession during a clock cycle of the external clock signal. The data is output synchronously with respect to the internal clock signal.

Abstract: The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention.

Abstract: A method of operation of a synchronous memory device. The memory device includes an array of dynamic random access memory cells. The method of operation of the memory device includes receiving an external clock signal, and sampling a first operation code synchronously with respect to the external clock signal, the first operation code specifying a write operation. Additionally, the method of operation of the memory device includes sampling data after a number of clock cycles of the external clock signal transpire. The data is sampled in response to the first operation code.

Abstract: An integrated circuit device which includes an array of dynamic memory cells. The integrated circuit device comprises an input receiver to sample an operation code synchronously with respect to a transition of a clock signal, the operation code indicating a read operation. The integrated circuit device also comprises an output driver to output data in response to the operation code, wherein the data is output after a number of clock cycles of the clock signal transpire.

Abstract: A synchronous memory device including an array of memory cells. The memory device includes a plurality of sense amplifiers, coupled to the array of memory cells, to sense data. The memory device further includes input receiver circuitry to sample an operation code synchronously with respect to a transition of an external clock signal. The operation code including precharge information and, in response to the precharge information, the plurality of sense amplifiers are automatically precharged after the data is sensed.

Abstract: A synchronous integrated circuit memory device including an array of memory cells. The memory device includes a clock receiver to receive an external clock signal, and a plurality of sense amplifiers, coupled to the array of memory cells, to sense data. A first portion of the data is output from the memory device in response to a first operation code bit specifying a read operation. In addition, the memory device includes a first input receiver to sample the first operation code bit in response to a first transition of the external clock signal. Furthermore, the memory device includes a second input receiver to sample a second operation code bit in response to the first transition of the external clock signal. The second operation code bit indicates whether precharging the plurality of sense amplifiers occurs automatically after the data has been sensed. Moreover, the memory device includes a plurality of output drivers to output the portion of the data synchronously with respect to the external clock signal.

Abstract: A memory device and a method of operation of the memory device. The memory device includes an array of memory cells and a reference voltage input terminal to receive an external reference voltage. In addition, the memory device includes an input receiver, coupled to the reference voltage input terminal, to sample data from an external signal line using the external reference voltage.

Abstract: The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices.

Abstract: The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices.

Abstract: The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices.

Abstract: A method of controlling a memory device, wherein the memory device includes a plurality of memory cells. The method includes providing first block size information to the memory device, wherein the first block size information defines a first amount of data to be input by the memory device in response to a write request. The method further includes issuing a write request to the memory device, wherein in response to the write request the memory device inputs the first amount of data corresponding to the first block size information.

Abstract: A synchronous memory device and methods of operation and controlling such a device. The method of controlling the memory device includes providing a value which is representative of a number of cycles of an external clock signal to transpire after which the memory device responds to a read request. The method further includes providing block size information to the memory device, wherein the block size information defines an amount of data to be output by the memory device in response to a read request. The method further includes receiving the amount of data, after the number of clock cycles of the external clock signal transpire.

Abstract: The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices.

Abstract: The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices.

Abstract: The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices.

Abstract: A synchronous memory device and a method of controlling the memory device. The memory device including at least one memory section having a plurality of memory cells. The memory device includes a first internal register to store a value which is indicative of a number of clock cycles to transpire before the memory device responds to a read request. The memory device also includes a second internal register to store an identification value to identify the memory device on a bus.

Abstract: A system and an integrated circuit device therefor. The integrated circuit device comprises output driver circuitry to output data onto a first external signal line. The output driver circuitry outputs a first portion of data in response to a rising edge transition of a first external clock signal. The output driver circuitry outputs a second portion of data in response to a falling edge transition of the first external clock signal. The integrated circuit device may further include input receiver circuitry to sample data from a second external signal line. The input receiver circuitry samples a first portion of data in response to a rising edge transition of a second external clock signal. The input receiver circuitry samples a second portion of data in response to a falling edge transition of the second external clock signal.

Abstract: The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices.