Patents by Inventor Mark Hummel

Mark Hummel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250133058
    Abstract: Systems and methods herein are for one or more processing units that can communicate in a network using a subnet manager (SM) that includes a mapping of one virtual network address to two or more physical ports, where the one virtual network address may be associated with different switches of different data planes, and where data may be communicated concurrently and separately using the one virtual network address and using the two or more physical ports.
    Type: Application
    Filed: October 23, 2023
    Publication date: April 24, 2025
    Inventors: Lior Hodaya Bezen, Alex Netes, Idan Seider, Lion Levi, Glenn Dearth, Nitin Hande, Mark Hummel
  • Publication number: 20250080460
    Abstract: Systems and methods herein are for one or more processing units to be associated with at least one switch or router and to enable the at least one switch or router to receive a communication from a source host machine, where the communication includes a request associated with memory access protocols of a memory space of a destination host machine, and where the communication is to be provided to the destination host machine to enable subsequent communications from the source host machine that are based in part on the memory access protocols received in response to the request.
    Type: Application
    Filed: August 31, 2023
    Publication date: March 6, 2025
    Inventors: Mark Hummel, Jonathan Mercer Owen, Gregory Thorson, Glenn Dearth, Lion Levi, Lior Hodaya Bezen, Itamar Rabenstein, Ami Gidon Marelli, Roee Levy Leshem, Liron Mula, Alex Netes, Eyal Srebro
  • Publication number: 20240406154
    Abstract: Technologies for encrypting communication links between devices are described. A method includes generating a first initialization vector (IV), from a first subspace of IVs, for a first cryptographic ordered flow, and a second IV, from a second subspace of IVs that are mutually exclusive from the first subspace. The first and second cryptographic ordered flows share a key to secure multipath routing in a fabric between devices. The method sends, to the second device, a first packet for the first cryptographic ordered flow and a second packet for the second cryptographic ordered flow. The first packet includes a first security tag with the first IV and a first payload encrypted using the first IV and a first key. The second packet includes a second security tag with the second IV and a second payload encrypted using the second IV and a second key.
    Type: Application
    Filed: December 4, 2023
    Publication date: December 5, 2024
    Inventors: Miriam Menes, Naveen Cherukuri, Ahmad Atamli, Uria Basher, Mike Osborn, Mark Hummel, Liron Mula
  • Publication number: 20240393951
    Abstract: Various embodiments include techniques for performing self-synchronizing remote memory operations in a multiprocessor computing system. During a remote memory operation in the multiprocessor computing system, a source processing unit transmits multiple segments of data to a destination processing. For each segment of data, the source processing unit transmits a remote memory operation to the destination processing unit that includes associated metadata that identifies the memory location of a corresponding synchronization object. The remote memory operation along with the metadata is transmitted as a single unit to the destination processing unit. The destination processing unit splits the operation into the remote memory operation and the memory synchronization operation. As a result, the source processing unit avoids the need to perform a separate memory synchronization operation, thereby reducing inter-processor communications and increasing performance of remote memory operations.
    Type: Application
    Filed: July 10, 2024
    Publication date: November 28, 2024
    Inventors: Srinivas Santosh Kumar MADUGULA, Olivier GIROUX, Wishwesh Anil GANDHI, Michael Allen PARKER, Raghuram L, Ivan TANASIC, Manan PATEL, Mark HUMMEL, Alexander L. MINKIN
  • Publication number: 20240354106
    Abstract: Various embodiments include techniques for performing self-synchronizing remote memory operations in a data center or multiprocessor computing system. During a remote memory operation, a source processor transmits multiple data segments to a destination processor. For each data segment, the source processor transmits a remote memory operation to the destination processor that includes associated metadata that identifies the memory location of a corresponding synchronization object representing a count of data segments to be stored or a flag for each data segment to be stored. The remote memory operation along with the metadata is transmitted as a single unit to the destination processor. The destination processor splits the operation into the remote memory operation and the memory synchronization operation.
    Type: Application
    Filed: June 26, 2024
    Publication date: October 24, 2024
    Inventors: Srinivas Santosh Kumar MADUGULA, Olivier GIROUX, Wishwesh Anil GANDHI, Michael Allen PARKER, Raghuram L, Ivan TANASIC, Manan PATEL, Mark HUMMEL, Alexander L. MINKIN, Gregory Michael THORSON
  • Patent number: 12105960
    Abstract: Various embodiments include techniques for performing self-synchronizing remote memory operations in a multiprocessor computing system. During a remote memory operation in the multiprocessor computing system, a source processing unit transmits multiple segments of data to a destination processing. For each segment of data, the source processing unit transmits a remote memory operation to the destination processing unit that includes associated metadata that identifies the memory location of a corresponding synchronization object. The remote memory operation along with the metadata is transmitted as a single unit to the destination processing unit. The destination processing unit splits the operation into the remote memory operation and the memory synchronization operation. As a result, the source processing unit avoids the need to perform a separate memory synchronization operation, thereby reducing inter-processor communications and increasing performance of remote memory operations.
    Type: Grant
    Filed: August 31, 2022
    Date of Patent: October 1, 2024
    Assignee: NVIDIA CORPORATION
    Inventors: Srinivas Santosh Kumar Madugula, Olivier Giroux, Wishwesh Anil Gandhi, Michael Allen Parker, Raghuram L, Ivan Tanasic, Manan Patel, Mark Hummel, Alexander L. Minkin
  • Publication number: 20240291757
    Abstract: Systems and methods herein are for one or more processing units to be associated with at least one switch or router of different route layers and to enable the at least one switch or router to receive a communication from a host machine, wherein the communication includes at least a data packet and a hash header, wherein the data packet is for transmission to other host machines through at least one of available egress ports of the at least one switch or router, and where the at least one of the available egress ports is determined based in part on a hash in the hash header.
    Type: Application
    Filed: February 23, 2023
    Publication date: August 29, 2024
    Inventors: Lior Hodaya Bezen, Gil Mey-Tal, Mark Hummel, Idan Seider, Alex Netes, Nitzan Reznik, Roee Levy Leshem, Lion Levi, Itamar Rabenstein
  • Publication number: 20240259234
    Abstract: Systems and methods herein are for one or more processing units to communicate configuration information between a subnet manager (SM) and at least one switch, where the configuration information is to enable the at least one switch to provide communication between at least two host machines through a number of network links that exclusively use two or more physical ports of the at least two host machines, and where the configuration information is associated with a mapping of different virtual network addresses and two or more physical ports and is associated with a relationship between the different virtual network addresses.
    Type: Application
    Filed: January 31, 2023
    Publication date: August 1, 2024
    Inventors: Lior Hodaya Bezen, Alex Netes, Mark Hummel, Glenn Dearth, Lion Levi
  • Publication number: 20240137410
    Abstract: Systems and techniques for performing multicast-reduction operations. In at least one embodiment, a network device receives first network data associated with a multicast operation to be collectively performed by at least a plurality of endpoints. The network device reserves resources to process second network data to be received from the endpoints, and sends the first network data to a plurality of additional network devices. The network device receives the second network data, and processes the second network data using the reserved resources.
    Type: Application
    Filed: December 19, 2023
    Publication date: April 25, 2024
    Inventors: Glenn Dearth, Mark Hummel, Nan Jiang, Gregory Thorson
  • Patent number: 11956306
    Abstract: Systems and techniques for performing multicast-reduction operations. In at least one embodiment, a network device receives first network data associated with a multicast operation to be collectively performed by at least a plurality of endpoints. The network device reserves resources to process second network data to be received from the endpoints, and sends the first network data to a plurality of additional network devices. The network device receives the second network data, and processes the second network data using the reserved resources.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: April 9, 2024
    Assignee: NVIDIA CORPORATION
    Inventors: Glenn Dearth, Mark Hummel, Nan Jiang, Gregory Thorson
  • Publication number: 20240098139
    Abstract: Systems and techniques for performing multicast-reduction operations. In at least one embodiment, a network device receives first network data associated with a multicast operation to be collectively performed by at least a plurality of endpoints. The network device reserves resources to process second network data to be received from the endpoints, and sends the first network data to a plurality of additional network devices. The network device receives the second network data, and processes the second network data using the reserved resources.
    Type: Application
    Filed: March 30, 2022
    Publication date: March 21, 2024
    Inventors: Glenn Dearth, Mark Hummel, Nan Jiang, Gregory Thorson
  • Publication number: 20240069736
    Abstract: Various embodiments include techniques for performing self-synchronizing remote memory operations in a multiprocessor computing system. During a remote memory operation in the multiprocessor computing system, a source processing unit transmits multiple segments of data to a destination processing. For each segment of data, the source processing unit transmits a remote memory operation to the destination processing unit that includes associated metadata that identifies the memory location of a corresponding synchronization object. The remote memory operation along with the metadata is transmitted as a single unit to the destination processing unit. The destination processing unit splits the operation into the remote memory operation and the memory synchronization operation. As a result, the source processing unit avoids the need to perform a separate memory synchronization operation, thereby reducing inter-processor communications and increasing performance of remote memory operations.
    Type: Application
    Filed: August 31, 2022
    Publication date: February 29, 2024
    Inventors: Srinivas Santosh Kumar MADUGULA, Olivier GIROUX, Wishwesh Anil GANDHI, Michael Allen PARKER, Raghuram L, Ivan TANASIC, Manan PATEL, Mark HUMMEL, Alexander L. MINKIN
  • Patent number: 11863390
    Abstract: Apparatuses, systems, and techniques are presented to configure computing resources to perform various tasks. In at least one embodiment, an approach presented herein can be used to verify whether a network of computing nodes is properly configured based, at least in part, on one or more expected data strings generated by the network of computing nodes.
    Type: Grant
    Filed: August 16, 2022
    Date of Patent: January 2, 2024
    Assignee: Nvidia Corporation
    Inventors: Miriam Menes, Eitan Zahavi, Gil Bloch, Ahmad Atamli, Meni Orenbach, Mark Hummel, Glenn Dearth
  • Publication number: 20230401159
    Abstract: A method and system for providing memory in a computer system. The method includes receiving a memory access request for a shared memory address from a processor, mapping the received memory access request to at least one virtual memory pool to produce a mapping result, and providing the mapping result to the processor.
    Type: Application
    Filed: August 24, 2023
    Publication date: December 14, 2023
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Anthony Asaro, Kevin Normoyle, Mark Hummel
  • Patent number: 11822491
    Abstract: Fabric Attached Memory (FAM) provides a pool of memory that can be accessed by one or more processors, such as a graphics processing unit(s) (GPU)(s), over a network fabric. In one instance, a technique is disclosed for using imperfect processors as memory controllers to allow memory, which is local to the imperfect processors, to be accessed by other processors as fabric attached memory. In another instance, memory address compaction is used within the fabric elements to fully utilize the available memory space.
    Type: Grant
    Filed: October 20, 2021
    Date of Patent: November 21, 2023
    Assignee: NVIDIA Corporation
    Inventors: John Feehrer, Denis Foley, Mark Hummel, Vyas Venkataraman, Ram Gummadi, Samuel H. Duncan, Glenn Dearth, Brian Kelleher
  • Patent number: 11741019
    Abstract: A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a plurality of processors. The method includes receiving a memory operation from a processor that references an address in a shared memory, mapping the received memory operation to at least one virtual memory pool to produce a mapping result, and providing the mapping result to the processor.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: August 29, 2023
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Anthony Asaro, Kevin Normoyle, Mark Hummel
  • Publication number: 20230229524
    Abstract: In various examples, a single notification (e.g., a request for a memory access operation) that a processing element (PE) has reached a synchronization barrier may be propagated to multiple physical addresses (PAs) and/or devices associated with multiple processing elements. Thus, the notification may allow an indication that the processing element has reached the synchronization barrier to be recoded at multiple targets. Each notification may access the PAs of each PE and/or device of a barrier group to update a corresponding counter. The PEs and/or devices may poll or otherwise use the counter to determine when each PE of the group has reached the synchronization barrier. When a corresponding counter indicates synchronization at the synchronization barrier, a PE may proceed with performing a compute task asynchronously with one or more other PEs until a subsequent synchronization barrier may be reached.
    Type: Application
    Filed: January 18, 2022
    Publication date: July 20, 2023
    Inventors: Glenn Alan Dearth, Mark Hummel, Daniel Joseph Lustig
  • Publication number: 20230229599
    Abstract: In various examples, a memory model may support multicasting where a single request for a memory access operation may be propagated to multiple physical addresses associated with multiple processing elements (e.g., corresponding to respective local memory). Thus, the request may cause data to be read from and/or written to memory for each of the processing elements. In some examples, a memory model exposes multicasting to processes. This may include providing for separate multicast and unicast instructions or shared instructions with one or more parameters (e.g., indicating a virtual address) being used to indicate multicasting or unicasting. Additionally or alternatively, whether a request(s) is processed using multicasting or unicasting may be opaque to a process and/or application or may otherwise be determined by the system. One or more constraints may be imposed on processing requests using multicasting to maintain a coherent memory interface.
    Type: Application
    Filed: January 18, 2022
    Publication date: July 20, 2023
    Inventors: Glenn Alan Dearth, Mark Hummel, Daniel Joseph Lustig
  • Publication number: 20230224239
    Abstract: Apparatuses, systems, and techniques to multicast a transaction to a group of targets. In at least one embodiment, a set is selected from alternate sets of directives associated with the group of targets, and the transaction is transmitted to the group of targets in accordance with the selected set.
    Type: Application
    Filed: January 13, 2022
    Publication date: July 13, 2023
    Inventors: Glenn Dearth, Nan Jiang, Mark Hummel, Richard Reeves
  • Publication number: 20220043759
    Abstract: Fabric Attached Memory (FAM) provides a pool of memory that can be accessed by one or more processors, such as a graphics processing unit(s) (GPU)(s), over a network fabric. In one instance, a technique is disclosed for using imperfect processors as memory controllers to allow memory, which is local to the imperfect processors, to be accessed by other processors as fabric attached memory. In another instance, memory address compaction is used within the fabric elements to fully utilize the available memory space.
    Type: Application
    Filed: October 20, 2021
    Publication date: February 10, 2022
    Inventors: John FEEHRER, Denis FOLEY, Mark HUMMEL, Vyas VENKATARAMAN, Ram GUMMADI, Samuel H. DUNCAN, Glenn DEARTH, Brian KELLEHER