Patents by Inventor Mark Hummel

Mark Hummel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10324860
    Abstract: A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a first processor configured for unified operation with a second processor. The method includes receiving a memory operation from a processor and mapping the memory operation to one of a plurality of memory heaps. The mapping produces a mapping result. The method also includes providing the mapping result to the processor.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: June 18, 2019
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Anthony Asaro, Kevin Normoyle, Mark Hummel
  • Patent number: 10200154
    Abstract: A receiver, transmitter and method for early packet header verification are provided. In one embodiment, the method includes: (1) receiving a payload flit of a preceding packet and a header flit of a current packet; and (2) using a Cyclic Redundancy Check (CRC) in the header flit to verify the payload flit of the preceding packet and the header flit of the current packet.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: February 5, 2019
    Assignee: Nvidia Corporation
    Inventors: Stephen D. Glaser, Eric Tyson, Mark Hummel, Michael Osborn, Jonathan Owen, Marvin Denman, Dennis Ma, Denis Foley
  • Publication number: 20180317545
    Abstract: Systems, methods, and devices for heat management of heating implements for a water pipe.
    Type: Application
    Filed: May 8, 2018
    Publication date: November 8, 2018
    Inventors: Reza Bavar, Tylor Garland, Michael Latham, Stephen Bradford, Richard Siemer, Mark Hummel, Wilson Reniers, Stephen Harper, Andrew Castro
  • Patent number: 10092034
    Abstract: A multi-chambered water pipe comprising an inner chamber and exterior chamber.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: October 9, 2018
    Assignee: KALOUD, INC.
    Inventors: Reza Bavar, Tylor Garland, Michael Latham, Stephen Bradford, Richard Siemer, Mark Hummel, Wilson Reniers, Stephen Harper, Andrew Castro
  • Patent number: 10097203
    Abstract: A CRC generator, a method for computing a CRC of a data packet, and an electronic system, such as a circuit board, are disclosed herein. In one embodiment the method is for computing the CRC of a data packet to be transmitted on a serial communications link having multiple lanes. In one embodiment, the CRC generator includes: (1) a CRC calculator configured to define a CRC calculation of a data packet in sequential order and perform parallelized computations, according to the sequential order and the multiple lanes, to generate sub-CRC values and (2) combination circuitry configured to combine the sub-CRC values to provide the CRC value for the packet.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: October 9, 2018
    Assignee: Nvidia Corporation
    Inventors: Eric Tyson, Stephen D. Glaser, Mike Osborn, Mark Hummel
  • Publication number: 20180213840
    Abstract: A multi-chambered water pipe comprising an inner chamber and exterior chamber.
    Type: Application
    Filed: February 1, 2017
    Publication date: August 2, 2018
    Inventors: Reza Bavar, Tylor Garland, Michael Latham, Stephen Bradford, Richard Seimer, Mark Hummel, Wilson Reniers, Stephen Harper, Andrew Castro
  • Publication number: 20180213841
    Abstract: A multi-chambered water pipe comprising an inner chamber and exterior chamber.
    Type: Application
    Filed: March 31, 2017
    Publication date: August 2, 2018
    Inventors: Reza Bavar, Tylor Garland, Michael Latham, Stephen Bradford, Richard Siemer, Mark Hummel, Wilson Reniers, Stephen Harper, Andrew Castro
  • Patent number: 10034491
    Abstract: A multi-chambered water pipe comprising an inner chamber and exterior chamber.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: July 31, 2018
    Assignee: KALOUD, INC.
    Inventors: Reza Bavar, Tylor Garland, Michael Latham, Stephen Bradford, Richard Seimer, Mark Hummel, Wilson Reniers, Stephen Harper, Andrew Castro
  • Patent number: 9965392
    Abstract: Existing multiprocessor computing systems often have insufficient memory coherency and, consequently, are unable to efficiently utilize separate memory systems. Specifically, a CPU cannot effectively write to a block of memory and then have a GPU access that memory unless there is explicit synchronization. In addition, because the GPU is forced to statically split memory locations between itself and the CPU, existing multiprocessor computing systems are unable to efficiently utilize the separate memory systems. Embodiments described herein overcome these deficiencies by receiving a notification within the GPU that the CPU has finished processing data that is stored in coherent memory, and invalidating data in the CPU caches that the GPU has finished processing from the coherent memory. Embodiments described herein also include dynamically partitioning a GPU memory into coherent memory and local memory through use of a probe filter.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: May 8, 2018
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Anthony Asaro, Kevin Normoyle, Mark Hummel
  • Patent number: 9954984
    Abstract: A receiver, transmitter and method for enabling a replay using a packetized link protocol are provided. In one embodiment, the method includes: (1) transmitting a stream of packets including an untagged packet and (2) using synchronized counters to determine a sequence ID of the untagged packet, which is a corrupt/lost packet that needs to be retransmitted.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: April 24, 2018
    Assignee: Nvidia Corporation
    Inventors: Dennis Ma, Michael Osborn, Eric Tyson, Stephen D. Glaser, Marvin Denman, Jonathan Owen, Mark Hummel
  • Publication number: 20180011798
    Abstract: A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a first processor configured for unified operation with a second processor. The method includes receiving a memory operation from a processor and mapping the memory operation to one of a plurality of memory heaps. The mapping produces a mapping result. The method also includes providing the mapping result to the processor.
    Type: Application
    Filed: September 5, 2017
    Publication date: January 11, 2018
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Anthony ASARO, Kevin NORMOYLE, Mark HUMMEL
  • Patent number: 9858221
    Abstract: Remotely synchronizing data communicated in an electronic computing system. Ordered writing of a data set of discrete data packets (data) and a following associated semaphore packet (semaphore) from a source electronic device (source) to a bridge interface device (bridge). Relaxed writing of the data set from the bridge to discrete target memory addresses (targets) of a data-consuming electronic device (consumer), wherein the order of the data and the semaphore written to the targets is different than the order of the data and semaphore written with the ordered writing. Monitoring, by the consumer, the relaxed writing of the semaphore to one of the targets. Issuing a synchronization command to the bridge upon detection of the semaphore having been written to the one target. Sending a synchronization confirmation reply from the bridge after all of the data has been written to the targets.
    Type: Grant
    Filed: February 15, 2016
    Date of Patent: January 2, 2018
    Assignee: Nvidia Corporation
    Inventors: Mike Osborn, Mark Hummel, Jonathan Owen, Samuel Hammond Duncan
  • Publication number: 20170288815
    Abstract: A receiver, transmitter and method for early packet header verification are provided. In one embodiment, the method includes: (1) receiving a payload flit of a preceding packet and a header flit of a current packet; and (2) using a Cyclic Redundancy Check (CRC) in the header flit to verify the payload flit of the preceding packet and the header flit of the current packet.
    Type: Application
    Filed: June 23, 2017
    Publication date: October 5, 2017
    Inventors: Stephen D. Glaser, Eric Tyson, Mark Hummel, Michael Osborn, Jonathan Owen, Marvin Denman, Dennis Ma, Denis Foley
  • Publication number: 20170235690
    Abstract: Remotely synchronizing data communicated in an electronic computing system. Ordered writing of a data set of discrete data packets (data) and a following associated semaphore packet (semaphore) from a source electronic device (source) to a bridge interface device (bridge). Relaxed writing of the data set from the bridge to discrete target memory addresses (targets) of a data-consuming electronic device (consumer), wherein the order of the data and the semaphore written to the targets is different than the order of the data and semaphore written with the ordered writing. Monitoring, by the consumer, the relaxed writing of the semaphore to one of the targets. Issuing a synchronization command to the bridge upon detection of the semaphore having been written to the one target. Sending a synchronization confirmation reply from the bridge after all of the data has been written to the targets.
    Type: Application
    Filed: February 15, 2016
    Publication date: August 17, 2017
    Inventors: Mike Osborn, Mark Hummel, Jonathan Owen, Samuel Hammond Duncan
  • Patent number: 9720768
    Abstract: A receiver, transmitter and method for early packet header verification are provided. In one embodiment, the method includes: (1) receiving a payload flit of a preceding packet and a header flit of a current packet; and (2) using a Cyclic Redundancy Check (CRC) in the header flit to verify the payload flit of the preceding packet and the header flit of the current packet.
    Type: Grant
    Filed: October 6, 2015
    Date of Patent: August 1, 2017
    Assignee: Nvidia Corporation
    Inventors: Stephen D. Glaser, Eric Tyson, Mark Hummel, Michael Osborn, Jonathan Owen, Marvin Denman, Dennis Ma, Denis Foley
  • Publication number: 20170141794
    Abstract: A CRC generator, a method for computing a CRC of a data packet, and an electronic system, such as a circuit board, are disclosed herein. In one embodiment the method is for computing the CRC of a data packet to be transmitted on a serial communications link having multiple lanes. In one embodiment, the CRC generator includes: (1) a CRC calculator configured to define a CRC calculation of a data packet in sequential order and perform parallelized computations, according to the sequential order and the multiple lanes, to generate sub-CRC values and (2) combination circuitry configured to combine the sub-CRC values to provide the CRC value for the packet.
    Type: Application
    Filed: November 12, 2015
    Publication date: May 18, 2017
    Inventors: Eric Tyson, Stephen D. Glaser, Mike Osborn, Mark Hummel
  • Publication number: 20170111144
    Abstract: A receiver, transmitter and method for enabling a replay using a packetized link protocol are provided. In one embodiment, the method includes: (1) transmitting a stream of packets including an untagged packet and (2) using synchronized counters to determine a sequence ID of the untagged packet, which is a corrupt/lost packet that needs to be retransmitted.
    Type: Application
    Filed: October 14, 2015
    Publication date: April 20, 2017
    Inventors: Dennis Ma, Michael Osborn, Eric Tyson, Stephen D. Glaser, Marvin Denman, Jonathan Owen, Mark Hummel
  • Publication number: 20170097867
    Abstract: A receiver, transmitter and method for early packet header verification are provided. In one embodiment, the method includes: (1) receiving a payload flit of a preceding packet and a header flit of a current packet; and (2) using a Cyclic Redundancy Check (CRC) in the header flit to verify the payload flit of the preceding packet and the header flit of the current packet.
    Type: Application
    Filed: October 6, 2015
    Publication date: April 6, 2017
    Inventors: Stephen D. Glaser, Eric Tyson, Mark Hummel, Michael Osborn, Jonathan Owen, Marvin Denman, Dennis Ma, Denis Foley
  • Patent number: 9606936
    Abstract: Methods, systems, and computer readable media generalize control registers in the context of memory address translations for I/O devices. A method includes maintaining a table including a plurality of concurrently available control register base pointers each associated with a corresponding input/output (I/O) device, associating each control register base pointer with a first translation from a guest virtual address (GVA) to a guest physical address (GPA) and a second translation from the GPA to a system physical address (SPA), and operating the first and second translations concurrently for the plurality of I/O devices.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: March 28, 2017
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Andy Kegel, Mark Hummel, Tony Asaro, Philip Ng
  • Publication number: 20160371197
    Abstract: A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a first processor configured for unified operation with a second processor. The method includes receiving a memory operation from a processor and mapping the memory operation to one of a plurality of memory heaps. The mapping produces a mapping result. The method also includes providing the mapping result to the processor.
    Type: Application
    Filed: September 1, 2016
    Publication date: December 22, 2016
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Anthony ASARO, Kevin NORMOYLE, Mark HUMMEL