Patents by Inventor Mark Hummel
Mark Hummel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9720768Abstract: A receiver, transmitter and method for early packet header verification are provided. In one embodiment, the method includes: (1) receiving a payload flit of a preceding packet and a header flit of a current packet; and (2) using a Cyclic Redundancy Check (CRC) in the header flit to verify the payload flit of the preceding packet and the header flit of the current packet.Type: GrantFiled: October 6, 2015Date of Patent: August 1, 2017Assignee: Nvidia CorporationInventors: Stephen D. Glaser, Eric Tyson, Mark Hummel, Michael Osborn, Jonathan Owen, Marvin Denman, Dennis Ma, Denis Foley
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Publication number: 20170141794Abstract: A CRC generator, a method for computing a CRC of a data packet, and an electronic system, such as a circuit board, are disclosed herein. In one embodiment the method is for computing the CRC of a data packet to be transmitted on a serial communications link having multiple lanes. In one embodiment, the CRC generator includes: (1) a CRC calculator configured to define a CRC calculation of a data packet in sequential order and perform parallelized computations, according to the sequential order and the multiple lanes, to generate sub-CRC values and (2) combination circuitry configured to combine the sub-CRC values to provide the CRC value for the packet.Type: ApplicationFiled: November 12, 2015Publication date: May 18, 2017Inventors: Eric Tyson, Stephen D. Glaser, Mike Osborn, Mark Hummel
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Publication number: 20170111144Abstract: A receiver, transmitter and method for enabling a replay using a packetized link protocol are provided. In one embodiment, the method includes: (1) transmitting a stream of packets including an untagged packet and (2) using synchronized counters to determine a sequence ID of the untagged packet, which is a corrupt/lost packet that needs to be retransmitted.Type: ApplicationFiled: October 14, 2015Publication date: April 20, 2017Inventors: Dennis Ma, Michael Osborn, Eric Tyson, Stephen D. Glaser, Marvin Denman, Jonathan Owen, Mark Hummel
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Publication number: 20170097867Abstract: A receiver, transmitter and method for early packet header verification are provided. In one embodiment, the method includes: (1) receiving a payload flit of a preceding packet and a header flit of a current packet; and (2) using a Cyclic Redundancy Check (CRC) in the header flit to verify the payload flit of the preceding packet and the header flit of the current packet.Type: ApplicationFiled: October 6, 2015Publication date: April 6, 2017Inventors: Stephen D. Glaser, Eric Tyson, Mark Hummel, Michael Osborn, Jonathan Owen, Marvin Denman, Dennis Ma, Denis Foley
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Patent number: 9606936Abstract: Methods, systems, and computer readable media generalize control registers in the context of memory address translations for I/O devices. A method includes maintaining a table including a plurality of concurrently available control register base pointers each associated with a corresponding input/output (I/O) device, associating each control register base pointer with a first translation from a guest virtual address (GVA) to a guest physical address (GPA) and a second translation from the GPA to a system physical address (SPA), and operating the first and second translations concurrently for the plurality of I/O devices.Type: GrantFiled: December 2, 2011Date of Patent: March 28, 2017Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Andy Kegel, Mark Hummel, Tony Asaro, Philip Ng
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Publication number: 20160371197Abstract: A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a first processor configured for unified operation with a second processor. The method includes receiving a memory operation from a processor and mapping the memory operation to one of a plurality of memory heaps. The mapping produces a mapping result. The method also includes providing the mapping result to the processor.Type: ApplicationFiled: September 1, 2016Publication date: December 22, 2016Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Anthony ASARO, Kevin NORMOYLE, Mark HUMMEL
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Publication number: 20160364334Abstract: Existing multiprocessor computing systems often have insufficient memory coherency and, consequently, are unable to efficiently utilize separate memory systems. Specifically, a CPU cannot effectively write to a block of memory and then have a GPU access that memory unless there is explicit synchronization. In addition, because the GPU is forced to statically split memory locations between itself and the CPU, existing multiprocessor computing systems are unable to efficiently utilize the separate memory systems. Embodiments described herein overcome these deficiencies by receiving a notification within the GPU that the CPU has finished processing data that is stored in coherent memory, and invalidating data in the CPU caches that the GPU has finished processing from the coherent memory. Embodiments described herein also include dynamically partitioning a GPU memory into coherent memory and local memory through use of a probe filter.Type: ApplicationFiled: August 24, 2016Publication date: December 15, 2016Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Anthony Asaro, Kevin Normoyle, Mark Hummel
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Patent number: 9448930Abstract: A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a first processor configured for unified operation with a second processor. The method includes receiving a memory operation from a processor and mapping the memory operation to one of a plurality of memory heaps. The mapping produces a mapping result. The method also includes providing the mapping result to the processor.Type: GrantFiled: August 24, 2015Date of Patent: September 20, 2016Assignee: Advanced Micro Devices, Inc.Inventors: Anthony Asaro, Kevin Normoyle, Mark Hummel
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Patent number: 9430391Abstract: Existing multiprocessor computing systems often have insufficient memory coherency and, consequently, are unable to efficiently utilize separate memory systems. Specifically, a CPU cannot effectively write to a block of memory and then have a GPU access that memory unless there is explicit synchronization. In addition, because the GPU is forced to statically split memory locations between itself and the CPU, existing multiprocessor computing systems are unable to efficiently utilize the separate memory systems. Embodiments described herein overcome these deficiencies by receiving a notification within the GPU that the CPU has finished processing data that is stored in coherent memory, and invalidating data in the CPU caches that the GPU has finished processing from the coherent memory. Embodiments described herein also include dynamically partitioning a GPU memory into coherent memory and local memory through use of a probe filter.Type: GrantFiled: August 31, 2012Date of Patent: August 30, 2016Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Anthony Asaro, Kevin Normoyle, Mark Hummel
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Patent number: 9253287Abstract: Described are a system and method for lossless message delivery between two processing devices. Each device includes a remote direct memory access (RDMA) messaging interface. The RDMA messaging interface at the first device generates one or more messages that are processed by the RDMA messaging interface of the second device. The RDMA messaging interface of the first device outputs a notification to the second device that a message of the one or more messages is available at the first device. A determination is made that the second device has resources to accommodate the message. The second device performs an operation in response to determining that the processing device has the resources to accommodate the message.Type: GrantFiled: August 20, 2012Date of Patent: February 2, 2016Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Venkata S. Krishnan, Mark Hummel, David E. Mayhew
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Publication number: 20150363310Abstract: A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a first processor configured for unified operation with a second processor. The method includes receiving a memory operation from a processor and mapping the memory operation to one of a plurality of memory heaps. The mapping produces a mapping result. The method also includes providing the mapping result to the processor.Type: ApplicationFiled: August 24, 2015Publication date: December 17, 2015Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Anthony ASARO, Kevin NORMOYLE, Mark HUMMEL
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Patent number: 9176794Abstract: A method, system, and computer program product are disclosed for providing improved access to accelerated processing device compute resources to user mode applications. The functionality disclosed allows user mode applications to provide commands to an accelerated processing device without the need for kernel mode transitions in order to access a unified ring buffer. Instead, applications are each provided with their own buffers, which the accelerated processing device hardware can access to process commands. With full operating system support, user mode applications are able to utilize the accelerated processing device in much the same way as a CPU.Type: GrantFiled: November 4, 2011Date of Patent: November 3, 2015Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Jeffrey Gongxian Cheng, Paul Blinzer, Mark Hummel, Leendert Peter Van Doorn
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Patent number: 9176795Abstract: A method, system, and computer program product are disclosed for providing improved access to accelerated processing device compute resources to user mode applications. The functionality disclosed allows user mode applications to provide commands to an accelerated processing device without the need for kernel mode transitions in order to access a unified ring buffer. Instead, applications are each provided with their own buffers, which the accelerated processing device hardware can access to process commands. With full operating system support, user mode applications are able to utilize the accelerated processing device in much the same way as a CPU.Type: GrantFiled: November 4, 2011Date of Patent: November 3, 2015Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Rex McCrary, Michael Houston, Philip J. Rogers, Gongxian Jeffrey Cheng, Mark Hummel, Paul Blinzer
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Patent number: 9154451Abstract: Described are systems and methods for communication between a plurality of electronic devices and an aggregation device. An aggregation device processes instructions related to a configuration of an electronic device in communication with the aggregation device. One or more virtual devices are generated in response to processing the instructions. The electronic device enumerates a configuration space to determine devices for use by the electronic device. The aggregation device detects an access of the configuration space by the electronic device. The one or more virtual devices are presented from the aggregation device to the electronic device in accordance with the instructions.Type: GrantFiled: August 21, 2012Date of Patent: October 6, 2015Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Anton Chernoff, Venkata S. Krishnan, Mark Hummel, David E. Mayhew, Michael J. Osborn
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Patent number: 9137173Abstract: Described are aggregation devices and methods for interconnecting server nodes. The aggregation device can include an input region, an output region, and a memory switch. The input region includes a plurality of input ports. The memory switch has a shared through silicon via (TSV) memory coupled to the input ports for temporarily storing data received at the input ports from a plurality of source devices. The output region includes a plurality of output ports coupled to the TSV memory. The output ports provide the data to a plurality of destination devices. A memory allocation system coordinates a transfer of the data from the source devices to the TSV memory. The output ports receive and process the data from the TSV memory independently of a communication from the input ports.Type: GrantFiled: June 19, 2012Date of Patent: September 15, 2015Assignee: ADVANCED MICRO DEVICES, INC.Inventors: David E. Mayhew, Mark Hummel, Michael J. Osborn
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Patent number: 9116809Abstract: A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a first processor configured for unified operation with a second processor. The method includes receiving a memory operation from a processor and mapping the memory operation to one of a plurality of memory heaps. The mapping produces a mapping result. The method also includes providing the mapping result to the processor.Type: GrantFiled: December 21, 2012Date of Patent: August 25, 2015Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.Inventors: Anthony Asaro, Kevin Normoyle, Mark Hummel
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Patent number: 8984511Abstract: Provided is a method of permitting the reordering of a visibility order of operations in a computer arrangement configured for permitting a first processor and a second processor threads to access a shared memory. The method includes receiving in a program order, a first and a second operation in a first thread and permitting the reordering of the visibility order for the operations in the shared memory based on the class of each operation. The visibility order determines the visibility in the shared memory, by a second thread, of stored results from the execution of the first and second operations.Type: GrantFiled: August 17, 2012Date of Patent: March 17, 2015Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Anthony Asaro, Kevin Normoyle, Mark Hummel
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Patent number: 8935475Abstract: Embodiments of the present invention provides for the execution of threads and/or workitems on multiple processors of a heterogeneous computing system in a manner that they can share data correctly and efficiently. Disclosed method, system, and article of manufacture embodiments include, responsive to an instruction from a sequence of instructions of a work-item, determining an ordering of visibility to other work-items of one or more other data items in relation to a particular data item, and performing at least one cache operation upon at least one of the particular data item or the other data items present in any one or more cache memories in accordance with the determined ordering. The semantics of the instruction includes a memory operation upon the particular data item.Type: GrantFiled: March 30, 2012Date of Patent: January 13, 2015Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.Inventors: Anthony Asaro, Kevin Normoyle, Mark Hummel, Norman Rubin, Mark Fowler
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Patent number: 8933947Abstract: Disclosed herein are systems, apparatuses, and methods for enabling efficient reads to a local memory of a processing unit. In an embodiment, a processing unit includes an interface and a buffer. The interface is configured to (i) send a request for a portion of data in a region of a local memory of an other processing unit and (ii) receive, responsive to the request, all the data from the region. The buffer is configured to store the data from the region of the local memory of the other processing unit.Type: GrantFiled: March 8, 2010Date of Patent: January 13, 2015Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.Inventors: David I. J. Glen, Philip J. Rogers, Gordon F. Caruk, Gongxian Jeffrey Cheng, Mark Hummel, Stephen Patrick Thompson, Anthony Asaro
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Patent number: 8879301Abstract: A method and apparatus for controlling state information retention determines at least a state information save or restore condition for at least one processing circuit such as one or more CPU or GPU cores or pipelines, in an integrated circuit. In response to determining the state information save or restore condition, the method and apparatus controls either or both of saving or restoring of state information for different virtual machines operating on the processing circuit, into corresponding on-die persistent passive variable resistance memory. The state information save or restore condition is a virtual machine level state information save or restore condition. State information for each of differing virtual machines is saved or restored from differing on-die passive variable resistance memory cells that are assigned on a per-virtual machine basis.Type: GrantFiled: September 14, 2012Date of Patent: November 4, 2014Assignee: Advanced Micro Devices, Inc.Inventors: David Mayhew, Mark Hummel, Michael Ignatowski