Patents by Inventor Mark Hummel

Mark Hummel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140068088
    Abstract: Described are a system and method for processing a media access control (MAC) address. A communication is established between a processing device and a network port of a data switching device. The data switching device assigns a MAC address to the processing device. The assigned MAC address is directly associated with the network port of the data switching device absent a learning mechanism.
    Type: Application
    Filed: September 4, 2012
    Publication date: March 6, 2014
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Venkata S. Krishnan, Anton Chernoff, Mark Hummel, David E. Mayhew
  • Publication number: 20140059160
    Abstract: Described are systems and methods for communication between a plurality of electronic devices and an aggregation device. An aggregation device processes instructions related to a configuration of an electronic device in communication with the aggregation device. One or more virtual devices are generated in response to processing the instructions. The electronic device enumerates a configuration space to determine devices for use by the electronic device. The aggregation device detects an access of the configuration space by the electronic device. The one or more virtual devices are presented from the aggregation device to the electronic device in accordance with the instructions.
    Type: Application
    Filed: August 21, 2012
    Publication date: February 27, 2014
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Anton Chernoff, Venkata S. Krishnan, Mark Hummel, David E. Mayhew, Michael J. Osborn
  • Publication number: 20140052808
    Abstract: Described are a system and method for lossless message delivery between two processing devices. Each device includes a remote direct memory access (RDMA) messaging interface. The RDMA messaging interface at the first device generates one or more messages that are processed by the RDMA messaging interface of the second device. The RDMA messaging interface of the first device outputs a notification to the second device that a message of the one or more messages is available at the first device. A determination is made that the second device has resources to accommodate the message. The second device performs an operation in response to determining that the processing device has the resources to accommodate the message.
    Type: Application
    Filed: August 20, 2012
    Publication date: February 20, 2014
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Venkata S. Krishnan, Mark Hummel, David E. Mayhew
  • Publication number: 20130346531
    Abstract: Described is an aggregation device comprising a plurality of virtual network interface cards (vNICs) and an input/output (I/O) processing complex. The vNICs are in communication with a plurality of processing devices. Each processing device has at least one virtual machine (VM). The I/O processing complex is between the vNICs and at least one physical NIC. The I/O processing complex includes at least one proxy NIC and a virtual switch. The virtual switch exchanges data with a processing device of the plurality of processing devices via a communication path established by a vNIC of the plurality of vNICs between the at least one VM and at least one proxy NIC.
    Type: Application
    Filed: June 25, 2012
    Publication date: December 26, 2013
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Mark Hummel, David E. Mayhew, Michael J. Osborn, Anton Chernoff, Venkata S. Krishnan
  • Patent number: 8615637
    Abstract: A processing system is provided. The processing system includes a first processing unit coupled to a first memory and a second processing unit coupled to a second memory. The second memory comprises a coherent memory and a private memory that is private to the second processing unit.
    Type: Grant
    Filed: September 9, 2010
    Date of Patent: December 24, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Philip J. Rogers, Warren Fritz Kruger, Mark Hummel, Eric Demers
  • Publication number: 20130339466
    Abstract: Described are aggregation devices and methods for interconnecting server nodes. The aggregation device can include an input region, an output region, and a memory switch. The input region includes a plurality of input ports. The memory switch has a shared through silicon via (TSV) memory coupled to the input ports for temporarily storing data received at the input ports from a plurality of source devices. The output region includes a plurality of output ports coupled to the TSV memory. The output ports provide the data to a plurality of destination devices. A memory allocation system coordinates a transfer of the data from the source devices to the TSV memory. The output ports receive and process the data from the TSV memory independently of a communication from the input ports.
    Type: Application
    Filed: June 19, 2012
    Publication date: December 19, 2013
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: David E. Mayhew, Mark Hummel, Michael J. Osborn
  • Publication number: 20130304841
    Abstract: Described are systems and methods for interconnecting devices. A switch fabric is in communication with a plurality of electronic devices. A rendezvous memory is in communication with the switch fabric. Data is transferred to the rendezvous memory from a first electronic device of the plurality of electronic devices in response to a determination that the data is ready for output from a memory at the first electronic device and in response to a location allocated in the rendezvous memory for the data.
    Type: Application
    Filed: May 14, 2012
    Publication date: November 14, 2013
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Mark Hummel, David E. Mayhew, Michael J. Osborn
  • Publication number: 20130262736
    Abstract: The present system enables receiving a request from an I/O device to translate a virtual address to a physical address to access the page in system memory. One or more memory attributes of the page defining a cacheability characteristic of the page is identified. A response including the physical address and the cacheability characteristic of the page is sent to the I/O device.
    Type: Application
    Filed: March 30, 2012
    Publication date: October 3, 2013
    Applicants: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Andrew KEGEL, Mark Hummel, Anthony Asaro
  • Publication number: 20130263141
    Abstract: Provided is a method of permitting the reordering of a visibility order of operations in a computer arrangement configured for permitting a first processor and a second processor threads to access a shared memory. The method includes receiving in a program order, a first and a second operation in a first thread and permitting the reordering of the visibility order for the operations in the shared memory based on the class of each operation. The visibility order determines the visibility in the shared memory, by a second thread, of stored results from the execution of the first and second operations.
    Type: Application
    Filed: August 17, 2012
    Publication date: October 3, 2013
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Anthony Asaro, Kevin Normoyle, Mark Hummel
  • Publication number: 20130262784
    Abstract: A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a first processor configured for unified operation with a second processor. The method includes receiving a memory operation from a processor and mapping the memory operation to one of a plurality of memory heaps. The mapping produces a mapping result. The method also includes providing the mapping result to the processor.
    Type: Application
    Filed: December 21, 2012
    Publication date: October 3, 2013
    Applicants: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Anthony Asaro, Kevin Normoyle, Mark Hummel
  • Publication number: 20130262776
    Abstract: Existing multiprocessor computing systems often have insufficient memory coherency and, consequently, are unable to efficiently utilize separate memory systems. Specifically, a CPU cannot effectively write to a block of memory and then have a GPU access that memory unless there is explicit synchronization. In addition, because the GPU is forced to statically split memory locations between itself and the CPU, existing multiprocessor computing systems are unable to efficiently utilize the separate memory systems. Embodiments described herein overcome these deficiencies by receiving a notification within the GPU that the CPU has finished processing data that is stored in coherent memory, and invalidating data in the CPU caches that the GPU has finished processing from the coherent memory. Embodiments described herein also include dynamically partitioning a GPU memory into coherent memory and local memory through use of a probe filter.
    Type: Application
    Filed: August 31, 2012
    Publication date: October 3, 2013
    Applicants: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Anthony ASARO, Kevin NORMOYLE, Mark HUMMEL
  • Publication number: 20130262775
    Abstract: Embodiments of the present invention provides for the execution of threads and/or workitems on multiple processors of a heterogeneous computing system in a manner that they can share data correctly and efficiently. Disclosed method, system, and article of manufacture embodiments include, responsive to an instruction from a sequence of instructions of a work-item, determining an ordering of visibility to other work-items of one or more other data items in relation to a particular data item, and performing at least one cache operation upon at least one of the particular data item or the other data items present in any one or more cache memories in accordance with the determined ordering. The semantics of the instruction includes a memory operation upon the particular data item.
    Type: Application
    Filed: March 30, 2012
    Publication date: October 3, 2013
    Applicants: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Anthony ASARO, Kevin Normoyle, Mark Hummel, Norman Rubin, Mark Fowler
  • Publication number: 20130262814
    Abstract: Embodiments of the present invention provide a method of a first processor using a memory resource associated with a second processor. The method includes receiving a memory instruction from a first processor process, wherein the memory instruction refers to a shared memory address (SMA) that maps to a second processor memory. The method also includes mapping the SMA to the second processor memory, wherein the mapping produces a mapping result and providing the mapping result to the first processor.
    Type: Application
    Filed: August 17, 2012
    Publication date: October 3, 2013
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Anthony Asaro, Kevin Normoyle, Mark Hummel
  • Publication number: 20130166834
    Abstract: A method and apparatus for managing a virtual address to physical address translation utilize a subpage level fault detecting and access. The method and apparatus may also use an additional subpage and page store Non-Volatile Store (NVS). The method and apparatus determines whether a page fault occurs or whether a subpage fault occurs to effect an address translation and also operates such that if a subpage fault had occurred, a subpage is loaded corresponding to the fault from a NVS to a DRAM, such as DRAM or any other suitable volatile memory historically referred to as main memory. The method and apparatus, if a page fault has occurred, determines if a page fault has occurred without operating system assistance and is a hardware page fault detection system that loads a page corresponding to the fault from NVS to DRAM.
    Type: Application
    Filed: December 21, 2011
    Publication date: June 27, 2013
    Applicant: Advanced Micro Devices, Inc.
    Inventors: David E. Mayhew, Mark Hummel
  • Publication number: 20130147821
    Abstract: In an embodiment, a method of processing memory requests in a first processing device is provided. The method includes generating a memory request associated with a memory address located in an unpinned memory space managed by an operating system running on a second processing device; and responsive to a determination that the memory address is not resident in a physical memory, transmitting a message to the second processing device. In response to the message, the operating system controls the second processing device to bring the memory address into the physical memory.
    Type: Application
    Filed: December 13, 2011
    Publication date: June 13, 2013
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Warren Fritz Kruger, Philip J. Rogers, Mark Hummel
  • Publication number: 20130145051
    Abstract: A system is enabled for configuring an IOMMU to provide direct access to system memory data by at least one I/O device/peripheral. Further, the IOMMU is configured to pass a pointer to at least one I/O device without having to translate the pointer. Further, commands are sent from a process within a guest operating system (OS) directly to a peripheral without intervention from a hypervisor. Further, the IOMMU is configured to grant peripherals access permissions to memory blocks to maintain isolation among peripherals.
    Type: Application
    Filed: December 2, 2011
    Publication date: June 6, 2013
    Inventors: Andrew Kegel, Mark Hummel
  • Publication number: 20130145055
    Abstract: The present system enables an input/output (I/O) device to request memory for performing a direct memory access (DMA) of system memory. Further, the system uses an input/output memory management unit (IOMMU) to determine whether or not the system memory is available. The IOMMU notifies an operating system associated with the system memory if the system memory is not available, such that the operating system allocates non-system memory for use by the I/O device to perform the DMA.
    Type: Application
    Filed: December 2, 2011
    Publication date: June 6, 2013
    Inventors: Andrew Kegel, Mark Hummel, Anthony Asaro, Phillip NG
  • Publication number: 20130138840
    Abstract: The present system enables passing a pointer, associated with accessing data in a memory, to an input/output (I/O) device via an input/output memory management unit (IOMMU). The I/O device accesses the data in the memory via the IOMMU without copying the data into a local I/O device memory. The I/O device can perform an operation on the data in the memory based on the pointer, such that I/O device accesses the memory without expensive copies.
    Type: Application
    Filed: November 30, 2011
    Publication date: May 30, 2013
    Inventors: Andrew Kegel, Mark Hummel, Anthony Asaro, Phillip Ng
  • Publication number: 20130070515
    Abstract: A method and apparatus for controlling state information retention determines at least a state information save or restore condition for at least one processing circuit such as one or more CPU or GPU cores or pipelines, in an integrated circuit. In response to determining the state information save or restore condition, the method and apparatus controls either or both of saving or restoring of state information for different virtual machines operating on the processing circuit, into corresponding on-die persistent passive variable resistance memory. The state information save or restore condition is a virtual machine level state information save or restore condition. State information for each of differing virtual machines is saved or restored from differing on-die passive variable resistance memory cells that are assigned on a per-virtual machine basis.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 21, 2013
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: David Mayhew, Mark Hummel, Michael Ignatowski
  • Publication number: 20120246381
    Abstract: Embodiments of the present invention provide methods, systems, and computer readable media for input output memory management unit (IOMMU) two-layer addressing in the context of memory address translations for I/O devices. According to an embodiment, a method includes translating a guest virtual address (GVA) to a corresponding guest physical address (GPA) using a guest address translation table according to a process address space identifier associated with an address translation transaction associated with an I/O device, and translating the GPA to a corresponding system physical address (SPA) using a system address translation table according to a device identifier associated with the address translation transaction.
    Type: Application
    Filed: December 2, 2011
    Publication date: September 27, 2012
    Inventors: Andy Kegel, Mark Hummel, Steve Glaser, Tony Asaro, Philip NG, Jeffrey Cheng