Patents by Inventor Mark Ish

Mark Ish has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200379684
    Abstract: A memory sub-system configured to predictively schedule the transfer of data to reduce idle time and the amount and time of data being buffered in the memory sub-system. For example, write commands received from a host system can be queued without buffering the data of the write commands at the same time. When executing a first write command using a media unit, the memory sub-system can predict a duration to a time the media unit becoming available for execution of a second write command. The communication of the data of the second command from the host system to a local buffer memory of the memory sub-system can be postponed and initiated according to the predicted duration. After the execution of the first write command, the second write command can be executed by the media unit without idling to store the data from the local buffer memory.
    Type: Application
    Filed: May 4, 2020
    Publication date: December 3, 2020
    Inventors: Sanjay Subbarao, Steven S. Williams, Mark Ish
  • Publication number: 20200363995
    Abstract: A memory sub-system configured to partially execute write commands from a host system to optimize performance. After receiving a write command from a host system, the memory sub-system can identify, based on a media physical layout, a preferred input/output size for the execution of the write command. The memory sub-system can execute the write command according to the preferred input/output size, configure a response for the write command to identify the second input/output size, and transmit the response identifying the second input/output size to the host system. The host system is configured to generate a subsequent write command to write at least the data that is initially identified in the write command that has been executed but not been included in the execution of the write command performed according to the preferred input/output size.
    Type: Application
    Filed: May 1, 2020
    Publication date: November 19, 2020
    Inventors: Sanjay Subbarao, Mark Ish
  • Publication number: 20200356307
    Abstract: A memory sub-system configured to dynamically determine input/output sizes of write commands based on a media physical layout of a memory sub-system. The memory sub-system can identify, dynamically in response to write commands being selected for execution in media units of the memory sub-system, a portion of a media layout that maps from logical addresses identified by the write commands in the logical address space to physical addresses of memory units in the media units. Based on the media layout, an input/output size for a next write command is identified and transmitted to the host system in a response. The host system generates the next write command and configures the amount of data to be written through the next write command based on based on the input/output size identified in the response.
    Type: Application
    Filed: May 1, 2020
    Publication date: November 12, 2020
    Inventors: Sanjay Subbarao, Mark Ish
  • Publication number: 20200293476
    Abstract: A first operation identifier is assigned to a current operation directed to a memory component, the first operation identifier having a first entry in a first data structure that associates the first operation identifier with a first buffer identifier. It is determined whether the current operation collides with a prior operation assigned a second operation identifier, the second operation identifier having a second entry in the first data structure that associates the second operation identifier with a second buffer identifier. A latest flag is updated to indicate that the first entry is a latest operation directed to an address (1) in response to determining that the current operation collides with the prior operation and that the current and prior operations are read operations, or (2) in response to determining to determining that the current operation does not collide with a prior operation.
    Type: Application
    Filed: May 28, 2020
    Publication date: September 17, 2020
    Inventors: Lyle E. Adams, Mark Ish, Pushpa Seetamraju, Karl D. Schuh, Dan Tupy
  • Patent number: 10754555
    Abstract: Method and apparatus for managing data in a memory, such as a flash memory. A memory module has a non-volatile memory (NVM) and a memory module electronics (MME) circuit configured to program data to and read data from solid-state non-volatile memory cells of the NVM. A map structure associates logical addresses of user data blocks with physical addresses in the NVM at which the user data blocks are stored. A controller circuit arranges the user data blocks into map units (MUs), and directs the MME circuit to write the MUs to a selected page of the NVM. The controller circuit updates the map structure to list only a single occurrence of a physical address for all of the MUs written to the selected page. The map structure is further updated to list an MU offset and an MU length for each of the MUs written to the selected page.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: August 25, 2020
    Assignee: Seagate Technology LLC
    Inventors: Timothy Canepa, Jeffrey Munsil, Jackson Ellis, Mark Ish
  • Patent number: 10739996
    Abstract: Systems and methods are disclosed for enhanced garbage collection operations at a memory device. The enhanced garbage collection may include selecting data and blocks to garbage collect to improve device performance. Data may be copied and reorganized according to a data stream via which the data was received, or data and blocks may be evaluated for garbage collection based on other access efficiency metrics. Data may be selected for collection based on sequentiality of the data, host access patterns, or other factors. Processing of host commands may be throttled based on a determined amount of work to garbage collect a plurality of blocks, in order to limit variability in host command throughput over a time period.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: August 11, 2020
    Assignee: Seagate Technology LLC
    Inventors: David Scott Ebsen, Kevin A Gomez, Mark Ish, Daniel John Benjamin, Robert Wayne Moss
  • Patent number: 10705996
    Abstract: A first operation identifier is assigned to a first operation directed to a memory component, the first operation identifier having an entry in a first data structure that associates the first operation identifier with a first plurality of buffer identifiers. It is determined whether the first operation collides with a prior operation assigned a second operation identifier, the second operation identifier having an entry in the first data structure that associates the second operation identifier with a second plurality of buffer identifiers. It is determined whether the first operation is a read or a write operation. In response to determining that the first operation collides with the prior operation and that the first operation is a read operation, the first plurality of buffer identifiers are updated with a buffer identifier included in the second plurality of buffer identifiers.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: July 7, 2020
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Lyle E. Adams, Mark Ish, Pushpa Seetamraju, Karl D. Schuh, Dan Tupy
  • Publication number: 20200192844
    Abstract: A first operation identifier is assigned to a first operation directed to a memory component, the first operation identifier having an entry in a first data structure that associates the first operation identifier with a first plurality of buffer identifiers. It is determined whether the first operation collides with a prior operation assigned a second operation identifier, the second operation identifier having an entry in the first data structure that associates the second operation identifier with a second plurality of buffer identifiers. It is determined whether the first operation is a read or a write operation. In response to determining that the first operation collides with the prior operation and that the first operation is a read operation, the first plurality of buffer identifiers are updated with a buffer identifier included in the second plurality of buffer identifiers.
    Type: Application
    Filed: November 25, 2019
    Publication date: June 18, 2020
    Inventors: Lyle E. Adams, Mark Ish, Pushpa Seetamraju, Karl D. Schuh, Dan Tupy
  • Patent number: 10635581
    Abstract: A garbage collection method comprises selecting one or blocks in a SSD of a hybrid drive for garbage collection; determining a state of data of the one or more selected blocks, wherein the state suggests a location and temperature of data; and executing a garbage collection efficiency and caching efficiency action on the data of the one or more selected blocks based on the determined state. The garbage collection process may utilize the state information provided by the cache layer of the hybrid drive to make decisions regarding data in the one or more selected blocks.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: April 28, 2020
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Alex Tang, Leonid Baryudin, Timothy Canepa, Mark Ish, Jackson Ellis
  • Patent number: 10564865
    Abstract: Method and apparatus for managing data in a distributed data storage system. In some embodiments, a plurality of storage devices define an overall available memory space. A control circuit stores a first copy of user data from a selected distributed data set in a working set of memory buffers, stores a duplicate, second copy of the user data in an alias set of memory buffers, generates parity data based on the second copy of the user data in the alias set of the memory buffers, and flushes the user data and the parity data from the alias set of memory buffers to the storage devices while the first copy of the user data remains in the working set of the memory buffers. In this way, subsequently received access commands can be serviced using the working set of the memory buffers.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: February 18, 2020
    Assignee: Seagate Technology LLC
    Inventors: Mark Ish, Anant Baderdinni, Balakrishnan Sundararaman, Shashank Nemawarkar
  • Patent number: 10558398
    Abstract: Systems and methods for reducing read latency by storing a redundant copy of data are described. In one embodiment, the systems and methods include identifying data assigned to be written to a page of a storage device, storing the data in a page of a first die of the storage device, and saving at least one codeword from the data to a page of a second die. In some embodiments, the first die is associated with a first channel of the storage device and the second die is associated with a second channel of the storage device.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: February 11, 2020
    Assignee: Seagate Technology LLC
    Inventors: Kevin A. Gomez, Mark Ish, David S. Ebsen, Daniel J. Benjamin
  • Patent number: 10559376
    Abstract: A data storage device can have at least a buffer memory, a selection module, and a non-volatile memory. The buffer memory and non-volatile memory may consist of different types of memory while the non-volatile memory has one or more rewritable in-place memory cells. The buffer memory and non-volatile memory may each store data associated with a pending data request as directed by the selection module until a settle time of the rewritable in-place memory cell has expired.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: February 11, 2020
    Assignee: Seagate Technology LLC
    Inventors: Timothy Canepa, Mark Ish, David S. Ebsen
  • Patent number: 10558380
    Abstract: Systems and methods for active power management are described. In one embodiment, the systems and methods include obtaining power dissipation metrics for a plurality of components under one or more operating scenarios, generating a reference dissipation model based on the power dissipation metrics of the plurality of components, and implementing the reference dissipation model in a storage system to make component scheduling decisions in relation to power management of the storage system. In some embodiments, the storage system includes any combination of a hard disk drive, a solid state drive, a hybrid drive, and a system of multiple storage drives.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: February 11, 2020
    Assignee: Seagate Technology LLC
    Inventors: David S. Ebsen, Kevin A. Gomez, Mark Ish, Daniel J. Benjamin
  • Patent number: 10534541
    Abstract: Method and apparatus for asynchronous discovery of processing and storage nodes coupled via an expander switch in a fabric. In some embodiments, an initiator device operates as a processing node to transfer data to and from a non-volatile memory (NVM) of a target device at a storage node. One of the initiator or target devices is activated prior to the other device. The second activated device broadcasts a discovery command responsive to the activation of the second activated device and prior to receipt of a request for the discovery command from the first activated device. The first activated device processes the discovery command to establish an I/O communication link between the first activated device and the second activated device. The discovery command may include a non-volatile memory express (NVMe) controller list, and the NVM may be arranged as one or more NVMe namespaces.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: January 14, 2020
    Assignee: Seagate Technology LLC
    Inventors: Mark Ish, Siddhartha Kumar Panda, Dileep Kumar Sharma, Durga Prasad Bhattarai
  • Patent number: 10521383
    Abstract: A first operation identifier is assigned to a first operation directed to a memory component, the first operation identifier having an entry in a first data structure that associates the first operation identifier with a first plurality of buffer identifiers. It is determined whether the first operation collides with a prior operation assigned a second operation identifier, the second operation identifier having an entry in the first data structure that associates the second operation identifier with a second plurality of buffer identifiers. It is determined whether the first operation is a read or a write operation. In response to determining that the first operation collides with the prior operation and that the first operation is a read operation, the first plurality of buffer identifiers are updated with a buffer identifier included in the second plurality of buffer identifiers.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: December 31, 2019
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Lyle E. Adams, Mark Ish, Pushpa Seetamraju, Karl D. Schuh, Dan Tupy
  • Publication number: 20190391886
    Abstract: Systems and methods for limiting performance variation in a storage device are described. Storage devices receive work requests to perform one or more operations from other computing devices, such as a host computing device. Completing the work requests may take a response time. In some embodiments, if the response time of executing the work request exceeds a threshold, the storage device may assign additional computing resources to complete the work request.
    Type: Application
    Filed: September 4, 2019
    Publication date: December 26, 2019
    Inventors: David S. Ebsen, Kevin A. Gomez, Mark Ish, Daniel J. Benjamin
  • Patent number: 10423500
    Abstract: Systems and methods for limiting performance variation in a storage device are described. Storage devices receive work requests to perform one or more operations from other computing devices, such as a host computing device. Completing the work requests may take a response time. In some embodiments, if the response time of executing the work request exceeds a threshold, the storage device may assign additional computing resources to complete the work request.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: September 24, 2019
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: David S. Ebsen, Kevin A. Gomez, Mark Ish, Daniel J. Benjamin
  • Patent number: 10394493
    Abstract: Apparatus and method for managing data in a hybrid data storage device. The device has a first non-volatile memory (NVM) of solid state memory cells arranged into a first set of garbage collection units (GCUs), and a second NVM as a rotatable data recording medium arranged into a second set of GCUs each comprising a plurality of shingled magnetic recording tracks. A control circuit combines a first group of logical block units (LBUs) stored in the first set of GCUs with a second group of LBUs stored in the second set of GCUs to form a combined group of LBUs arranged in sequential order by logical address. The control circuit streams the combined group of LBUs to a zone of shingled magnetic recording tracks in a selected one of the second set of GCUs. A combined media translation map identifies physical addresses in both the first and second NVMs.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: August 27, 2019
    Assignee: Seagate Technology LLC
    Inventors: Alex Tang, Leonid Baryudin, Michael Scott Hicken, Mark Ish, Carl Forhan
  • Patent number: 10310975
    Abstract: The disclosed technology provides for selection of a subset of available non-volatile memory devices in an array to receive a dirty cache data of a volatile cache responsive to detection of a power failure. In one implementation, the selection of the non-volatile memory devices is based on one or more predictive power parameters usable to estimate a time remaining during which a reserve power supply can support a cache offload to the selected subset of devices.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: June 4, 2019
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Shashank Nemawarkar, Balakrishnan Sundararaman, Mark Ish, Siddhartha Kumar Panda, Bagavathy Raj Arunachalam
  • Patent number: 10275361
    Abstract: Apparatus and method for managing namespaces in a Non-Volatile Memory Express (NVMe) controller environment. A non-volatile memory (NVM) is arranged to store map units (MUs) as addressable data blocks in one or more namespaces. A forward map has a sequence of map unit address (MUA) entries that correlate each of the MUs with the physical locations in the NVM. The MUA entries are grouped into immediately adjacent, contiguous ranges for each of the namespaces. A base MUA array identifies the address, within the forward map, of the beginning MUA entry for each namespace. A new namespace may be added by appending a new range of the MUA entries to the forward map immediate following the last MUA entry, and by adding a new entry to the base MUA array to identify the address, within the forward map, of the beginning MUA entry for the new namespace.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: April 30, 2019
    Assignee: Seagate Technology LLC
    Inventors: Mark Ish, Steven S. Williams, Jeffrey Munsil