Abstract: A total read counter, a plurality of die read counters, and a plurality of block read counters are maintained. Each die read counter is associated with a respective die of a memory device. A value of a block read counter and a value of a die read counter are determined for a specified block. Based on the value of the block read counter, the value of the die read counter, and the value of the total read counter, an estimated number of read events associated with the specified block of the memory device is determined. Responsive to determining that the estimated number of read events satisfies a predefined criterion, a media management operation of one or more pages associated with the specified block is performed.

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to receive a read command specifying an identifier of a logical block and a page number; translate the identifier of the logical block into a physical address of a physical block stored on the memory device, wherein the physical address comprises an identifier of a memory device die; identify, based on block family metadata associated with the memory device, a block family associated with the physical block and the page number; determine a threshold voltage offset associated with the block family and the memory device die; compute a modified threshold voltage by applying the threshold voltage offset to a base read level voltage associated with the memory device die; and read, using the modified threshold voltage, data from a physical page identified by the page number within the physical block.

Abstract: A total read counter, a plurality of die read counters, and a plurality of block read counters are maintained. Each die read counter is associated with a respective die of a memory device. A value of a block read counter and a value of a die read counter are determined for a specified block. Based on the value of the block read counter, the value of the die read counter, and the value of the total read counter, an estimated number of read events associated with the specified block of the memory device is determined. Responsive to determining that the estimated number of read events satisfies a predefined criterion, a media management operation of one or more pages associated with the specified block is performed.

Abstract: A memory sub-system having memory cells formed on a plurality of integrated circuit dies. After receiving a command from a host system to store data, the memory sub-system queues the command to allocate pages of memory cells in a plurality of dies in the plurality of integrated circuit dies based on a determination that each of the plurality of dies is available to perform a data programming operation for the command. Based on the page application, the memory sub-system generates a portion of a media layout to at least map logical addresses of the data identified in the command to the allocated pages and receives the data from the host system. The memory sub-system stores the data into the pages using a multi-pass programming technique, where an atomic multi-pass programming operation can be configured to use at least two pages in separate planes in one or more dies in the plurality of integrated circuit dies to program at least a portion of the data.

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to receive a read command specifying an identifier of a logical block and a page number; translate the identifier of the logical block into a physical address of a physical block stored on the memory device, wherein the physical address comprises an identifier of a memory device die; identify, based on block family metadata associated with the memory device, a block family associated with the physical block and the page number; determine a threshold voltage offset associated with the block family and the memory device die; compute a modified threshold voltage by applying the threshold voltage offset to a base read level voltage associated with the memory device die; and read, using the modified threshold voltage, data from a physical page identified by the page number within the physical block.

Abstract: A system includes integrated circuit (IC) dies having memory cells and a processing device, which is to perform operations including generating a number of zone map entries for zones of a logical block address (LBA) space that are sequentially mapped to physical address space of the plurality of IC dies, wherein each zone map entry corresponds to a respective data group that has been sequentially written to one or more IC dies; and generating a die identifier and a block identifier for each data block of multiple data blocks of the respective data group, wherein each data block corresponds to a media block of the plurality of IC dies.

Abstract: A memory sub-system configured to dynamically determine input/output sizes of write commands based on a media physical layout of a memory sub-system. The memory sub-system can identify, dynamically in response to write commands being selected for execution in media units of the memory sub-system, a portion of a media layout that maps from logical addresses identified by the write commands in the logical address space to physical addresses of memory units in the media units. Based on the media layout, an input/output size for a next write command is identified and transmitted to the host system in a response. The host system generates the next write command and configures the amount of data to be written through the next write command based on based on the input/output size identified in the response.

Abstract: A hybrid storage device with three-level memory mapping is provided. An illustrative device comprises a primary storage device comprising a plurality of primary sub-blocks; a cache memory device comprising a plurality of cache sub-blocks implemented as a cache for the primary storage device; and a controller configured to map at least one portion of one or more primary sub-blocks of the primary storage device stored in the cache to a physical location in the cache memory device using at least one table identifying portions of the primary storage device that are cached in one or more of the cache sub-blocks of the cache memory device, wherein a size of the at least one table is independent of a capacity of the primary storage device.

Abstract: A memory sub-system having memory cells formed on a plurality of integrated circuit dies. After receiving a command from a host system to store data, the memory sub-system queues the command to allocate pages of memory cells in a plurality of dies in the plurality of integrated circuit dies based on a determination that each of the plurality of dies is available to perform a data programming operation for the command. Based on the page application, the memory sub-system generates a portion of a media layout to at least map logical addresses of the data identified in the command to the allocated pages and receives the data from the host system. The memory sub-system stores the data into the pages using a multi-pass programming technique, where an atomic multi-pass programming operation can be configured to use at least two pages in separate planes in one or more dies in the plurality of integrated circuit dies to program at least a portion of the data.

Abstract: A system includes integrated circuit (IC) dies having memory cells and a processing device coupled to the IC dies. The processing device performs operations including storing, within a zone map data structure, zones of a logical block address (LBA) space sequentially mapped to physical address space of the IC dies. A zone map entry in the zone map data structure corresponds to a data group written to one or more of the IC dies. The operations further include storing, within a block set data structure indexed by a block set identifier of the zone map entry, a die identifier and a block identifier for each data block of multiple data blocks of the data group, and writing multiple data groups, which are sequentially mapped across the zones, sequentially across the IC dies. Each data block can correspond to a media (or erase) block of the IC dies.

Abstract: Methods, systems, and devices for metadata indication are described herein. A method includes receiving, from a host system, a read command to retrieve information from a first block of a memory device, identifying a transfer unit associated with the first block indicated in the read command, identifying an indicator in metadata of the identified transfer unit indicating that at least one sector of the transfer unit has been altered based at least in part on identifying the transfer unit, validating data of the transfer unit stored in the memory device based at least in part on identifying the indicator in the metadata, and retrieving the information stored in the first block based at least in part on validating the data of the transfer unit.

Abstract: A hybrid storage device with three-level memory mapping is provided. An illustrative device comprises a primary storage device comprising a plurality of primary sub-blocks; a cache memory device comprising a plurality of cache sub-blocks implemented as a cache for the primary storage device; and a controller configured to map at least one portion of one or more primary sub-blocks of the primary storage device stored in the cache to a physical location in the cache memory device using at least one table identifying portions of the primary storage device that are cached in one or more of the cache sub-blocks of the cache memory device, wherein a size of the at least one table is independent of a capacity of the primary storage device.

Abstract: Systems and methods for limiting performance variation in a storage device are described. Storage devices receive work requests to perform one or more operations from other computing devices, such as a host computing device. Completing the work requests may take a response time. In some embodiments, if the response time of executing the work request exceeds a threshold, the storage device may assign additional computing resources to complete the work request.

Abstract: Methods, systems, and devices for clock domain crossing queue are described. A memory sub-system can generate a namespace map having a set of namespace blocks associated with a memory sub-system. The namespace blocks can include one or more logical block addresses associated with the memory sub-system. One namespace block of the set of namespace blocks can include an indication that can indicate that the namespace block and each namespace block following the namespace block are available for mapping. The memory sub-system can receive a request to create a namespace and sequentially map one or more available namespace blocks to the namespace according to the ordering of the namespace map, including the namespace block with the indication.

Abstract: A memory sub-system configured to dynamically determine input/output sizes of write commands based on a media physical layout of a memory sub-system. The memory sub-system can identify, dynamically in response to write commands being selected for execution in media units of the memory sub-system, a portion of a media layout that maps from logical addresses identified by the write commands in the logical address space to physical addresses of memory units in the media units. Based on the media layout, an input/output size for a next write command is identified and transmitted to the host system in a response. The host system generates the next write command and configures the amount of data to be written through the next write command based on the input/output size identified in the response.

Abstract: A memory sub-system configured to partially execute write commands from a host system to optimize performance. After receiving a write command from a host system, the memory sub-system can identify, based on a media physical layout, a preferred input/output size for the execution of the write command. The memory sub-system can execute the write command according to the preferred input/output size, configure a response for the write command to identify the second input/output size, and transmit the response identifying the second input/output size to the host system. The host system is configured to generate a subsequent write command to write at least the data that is initially identified in the write command that has been executed but not been included in the execution of the write command performed according to the preferred input/output size.

Abstract: A request to perform a program operation at a memory device is received. Whether a firmware block record is to be modified to correspond with a device block record is determined based on parameters associated with the program operation. The firmware block record tracks entries of the device block record. Responsive to determining that the firmware block record is to be modified, the firmware block record is modified to correspond with the device block record.

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to receive a read command specifying an identifier of a logical block and a page number; translate the identifier of the logical block into a physical address of a physical block stored on the memory device, wherein the physical address comprises an identifier of a memory device die; identify, based on block family metadata associated with the memory device, a block family associated with the physical block and the page number; determine a threshold voltage offset associated with the block family and the memory device die; compute a modified threshold voltage by applying the threshold voltage offset to a base read level voltage associated with the memory device die; and read, using the modified threshold voltage, data from a physical page identified by the page number within the physical block.

Abstract: Methods, systems, and devices for sequential prefetching through a linking array are described. A prefetch manager can detect that a set of tags occupying a queue of a memory sub-system corresponds to a single read descriptor indicating a sequential read pattern. The prefetch manager can determine that a number of the set of tags occupying the queue is below a queue threshold and store data associated with at least one tag of the set of tags in an internal performance memory of the memory sub-system based on the detecting and the determining. In such cases, the prefetch manager can prefetch data from a memory manager and store in the internal performance memory.

Abstract: A request to perform a program operation at a memory device is received. An entry of a device block record stored at the memory device is determined to be removed based on parameters associated with the program operation and a firmware block record that corresponds to the device block record. The firmware block record tracks the entries of the device block record. The entries of the device block record are associated with blocks of the memory device and identify start voltages that are applied to wordlines of the blocks to program memory cells associated with the wordlines. A command is submitted to the memory device to remove the entry associated with a particular block from the device block record and to make a space available at the device block record for a new entry associated with a new block that is to be written in view of the program operation.