Abstract: A request to perform a program operation at a memory device is received. An entry of a device block record stored at the memory device is determined to be removed based on parameters associated with the program operation and a firmware block record that corresponds to the device block record. The firmware block record tracks the entries of the device block record. The entries of the device block record are associated with blocks of the memory device and identify start voltages that are applied to wordlines of the blocks to program memory cells associated with the wordlines. A command is submitted to the memory device to remove the entry associated with a particular block from the device block record and to make a space available at the device block record for a new entry associated with a new block that is to be written in view of the program operation.

Abstract: Methods, systems, and devices for metadata indication are described herein. A method includes receiving, from a host system, a read command to retrieve information from a first block of a memory device, identifying a transfer unit associated with the first block indicated in the read command, identifying an indicator in metadata of the identified transfer unit indicating that at least one sector of the transfer unit has been altered based at least in part on identifying the transfer unit, validating data of the transfer unit stored in the memory device based at least in part on identifying the indicator in the metadata, and retrieving the information stored in the first block based at least in part on validating the data of the transfer unit.

Abstract: An example method of generating an execution profile of a firmware module comprises: receiving an execution trace of a firmware module comprising a plurality of executable instructions, wherein the execution trace comprises a plurality of execution trace records, wherein each execution trace record of the plurality of execution trace records indicates a successful execution of an executable instruction identified by a program counter (PC) value; retrieving a first execution trace record of the plurality of execution trace records, wherein the first execution trace record comprises a first PC value; identifying a first executable instruction referenced by the first PC value; identifying a firmware function containing the first executable instruction; incrementing a cycle count for the firmware function by a number of cycles associated with the first executable instruction; and generating, using the cycle count, an execution profile of the firmware module.

Abstract: A system includes integrated circuit (IC) dies having memory cells and a processing device coupled to the IC dies. The processing device performs operations including storing, within a zone map data structure, zones of a logical block address (LBA) space sequentially mapped to physical address space of the IC dies. A zone map entry in the zone map data structure corresponds to a data group written to one or more of the IC dies. The operations further include storing, within a block set data structure indexed by a block set identifier of the zone map entry, a die identifier and a block identifier for each data block of multiple data blocks of the data group, and writing multiple data groups, which are sequentially mapped across the zones, sequentially across the IC dies. Each data block can correspond to a media (or erase) block of the IC dies.

Abstract: A request to read data from a location associated with a memory component is received. The request is assigned a first tag, the first tag having a first identifier of a first buffer to store data read from the location. The request to read data is determined to collide with an earlier request to write data to the location. The earlier request is assigned a second tag, the second tag having a second identifier of a second buffer to store data to write to the location. An attempt to lock the second tag and the second buffer for the request to read data is made. The request to read data is fulfilled from the second buffer in response to a successful attempt to lock the second tag and the second buffer.

Abstract: A first operation identifier is assigned to a current operation directed to a memory component, the first operation identifier having a first entry in a first data structure that associates the first operation identifier with a first buffer identifier. It is determined whether the current operation collides with a prior operation assigned a second operation identifier, the second operation identifier having a second entry in the first data structure that associates the second operation identifier with a second buffer identifier. A latest flag is updated to indicate that the first entry is a latest operation directed to an address (1) in response to determining that the current operation collides with the prior operation and that the current and prior operations are read operations, or (2) in response to determining to determining that the current operation does not collide with a prior operation.

Abstract: A first operation identifier is assigned to a current operation directed to a memory component, the first operation identifier having a first entry in a first data structure that associates the first operation identifier with a first buffer identifier. It is determined whether the current operation collides with a prior operation assigned a second operation identifier, the second operation identifier having a second entry in the first data structure that associates the second operation identifier with a second buffer identifier. A latest flag is updated to indicate that the first entry is a latest operation directed to an address (1) in response to determining that the current operation collides with the prior operation and that the current and prior operations are read operations, or (2) in response to determining to determining that the current operation does not collide with a prior operation.

Abstract: A request to read data from a location associated with a memory component is received. The request is assigned a first tag, the first tag having a first identifier of a first buffer to store data read from the location. The request to read data is determined to collide with an earlier request to write data to the location. The earlier request is assigned a second tag, the second tag having a second identifier of a second buffer to store data to write to the location. An attempt to lock the second tag and the second buffer for the request to read data is made. The request to read data is fulfilled from the second buffer in response to a successful attempt to lock the second tag and the second buffer.

Abstract: A memory sub-system having memory cells formed on a plurality of integrated circuit dies. After receiving a command from a host system to store data, the memory sub-system queues the command to allocate pages of memory cells in a plurality of dies in the plurality of integrated circuit dies based on a determination that each of the plurality of dies is available to perform a data programming operation for the command. Based on the page application, the memory sub-system generates a portion of a media layout to at least map logical addresses of the data identified in the command to the allocated pages and receives the data from the host system. The memory sub-system stores the data into the pages using a multi-pass programming technique, where an atomic multi-pass programming operation can be configured to use at least two pages in separate planes in one or more dies in the plurality of integrated circuit dies to program at least a portion of the data.

Abstract: A request to read data from a location associated with a memory component is received. The request is assigned a first tag, the first tag having a first identifier of a first buffer to store data read from the location. The request to read data is determined to collide with an earlier request to write data to the location. The earlier request is assigned a second tag, the second tag having a second identifier of a second buffer to store data to write to the location. An attempt to lock the second tag and the second buffer for the request to read data is made. The request to read data is fulfilled from the second buffer in response to a successful attempt to lock the second tag and the second buffer.

Abstract: A memory sub-system configured to predictively schedule the transfer of data to reduce idle time and the amount and time of data being buffered in the memory sub-system. For example, write commands received from a host system can be queued without buffering the data of the write commands at the same time. When executing a first write command using a media unit, the memory sub-system can predict a duration to a time the media unit becoming available for execution of a second write command. The communication of the data of the second command from the host system to a local buffer memory of the memory sub-system can be postponed and initiated according to the predicted duration. After the execution of the first write command, the second write command can be executed by the media unit without idling to store the data from the local buffer memory.

Abstract: A memory sub-system configured to partially execute write commands from a host system to optimize performance. After receiving a write command from a host system, the memory sub-system can identify, based on a media physical layout, a preferred input/output size for the execution of the write command. The memory sub-system can execute the write command according to the preferred input/output size, configure a response for the write command to identify the second input/output size, and transmit the response identifying the second input/output size to the host system. The host system is configured to generate a subsequent write command to write at least the data that is initially identified in the write command that has been executed but not been included in the execution of the write command performed according to the preferred input/output size.

Abstract: A memory sub-system configured to dynamically determine input/output sizes of write commands based on a media physical layout of a memory sub-system. The memory sub-system can identify, dynamically in response to write commands being selected for execution in media units of the memory sub-system, a portion of a media layout that maps from logical addresses identified by the write commands in the logical address space to physical addresses of memory units in the media units. Based on the media layout, an input/output size for a next write command is identified and transmitted to the host system in a response. The host system generates the next write command and configures the amount of data to be written through the next write command based on based on the input/output size identified in the response.

Abstract: A first operation identifier is assigned to a current operation directed to a memory component, the first operation identifier having a first entry in a first data structure that associates the first operation identifier with a first buffer identifier. It is determined whether the current operation collides with a prior operation assigned a second operation identifier, the second operation identifier having a second entry in the first data structure that associates the second operation identifier with a second buffer identifier. A latest flag is updated to indicate that the first entry is a latest operation directed to an address (1) in response to determining that the current operation collides with the prior operation and that the current and prior operations are read operations, or (2) in response to determining to determining that the current operation does not collide with a prior operation.

Abstract: Method and apparatus for managing data in a memory, such as a flash memory. A memory module has a non-volatile memory (NVM) and a memory module electronics (MME) circuit configured to program data to and read data from solid-state non-volatile memory cells of the NVM. A map structure associates logical addresses of user data blocks with physical addresses in the NVM at which the user data blocks are stored. A controller circuit arranges the user data blocks into map units (MUs), and directs the MME circuit to write the MUs to a selected page of the NVM. The controller circuit updates the map structure to list only a single occurrence of a physical address for all of the MUs written to the selected page. The map structure is further updated to list an MU offset and an MU length for each of the MUs written to the selected page.

Abstract: Systems and methods are disclosed for enhanced garbage collection operations at a memory device. The enhanced garbage collection may include selecting data and blocks to garbage collect to improve device performance. Data may be copied and reorganized according to a data stream via which the data was received, or data and blocks may be evaluated for garbage collection based on other access efficiency metrics. Data may be selected for collection based on sequentiality of the data, host access patterns, or other factors. Processing of host commands may be throttled based on a determined amount of work to garbage collect a plurality of blocks, in order to limit variability in host command throughput over a time period.

Abstract: A first operation identifier is assigned to a first operation directed to a memory component, the first operation identifier having an entry in a first data structure that associates the first operation identifier with a first plurality of buffer identifiers. It is determined whether the first operation collides with a prior operation assigned a second operation identifier, the second operation identifier having an entry in the first data structure that associates the second operation identifier with a second plurality of buffer identifiers. It is determined whether the first operation is a read or a write operation. In response to determining that the first operation collides with the prior operation and that the first operation is a read operation, the first plurality of buffer identifiers are updated with a buffer identifier included in the second plurality of buffer identifiers.

Abstract: A first operation identifier is assigned to a first operation directed to a memory component, the first operation identifier having an entry in a first data structure that associates the first operation identifier with a first plurality of buffer identifiers. It is determined whether the first operation collides with a prior operation assigned a second operation identifier, the second operation identifier having an entry in the first data structure that associates the second operation identifier with a second plurality of buffer identifiers. It is determined whether the first operation is a read or a write operation. In response to determining that the first operation collides with the prior operation and that the first operation is a read operation, the first plurality of buffer identifiers are updated with a buffer identifier included in the second plurality of buffer identifiers.

Abstract: A garbage collection method comprises selecting one or blocks in a SSD of a hybrid drive for garbage collection; determining a state of data of the one or more selected blocks, wherein the state suggests a location and temperature of data; and executing a garbage collection efficiency and caching efficiency action on the data of the one or more selected blocks based on the determined state. The garbage collection process may utilize the state information provided by the cache layer of the hybrid drive to make decisions regarding data in the one or more selected blocks.

Abstract: Method and apparatus for managing data in a distributed data storage system. In some embodiments, a plurality of storage devices define an overall available memory space. A control circuit stores a first copy of user data from a selected distributed data set in a working set of memory buffers, stores a duplicate, second copy of the user data in an alias set of memory buffers, generates parity data based on the second copy of the user data in the alias set of the memory buffers, and flushes the user data and the parity data from the alias set of memory buffers to the storage devices while the first copy of the user data remains in the working set of the memory buffers. In this way, subsequently received access commands can be serviced using the working set of the memory buffers.