Patents by Inventor Mark Ish

Mark Ish has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8321635
    Abstract: A method and apparatus for synchronizing input/output commands is provided. An incoming command mask representing an incoming input/output command associated with a memory region is created. In response to a determination that a pending input/output command associated with the memory region is pending, a bitwise inversion operation is performed on the incoming command mask to form a modified incoming command mask. A bitwise AND operation is performed on the modified incoming command mask and the pending command mask to form a pending command locking mask associated with the pending input/output command. A bitwise OR operation is performed between an existing memory lock for a same type of commands and incoming command bit mask to form a new memory region lock.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: November 27, 2012
    Assignee: LSI Corporation
    Inventor: Mark Ish
  • Publication number: 20120117297
    Abstract: Disclosed is a method of storage tiering with minimal use of DRAM memory for header overhead that utilizes the beginning of the volume to store frequently accessed or hot data. A solid state storage device is placed at the beginning of a tiered volume and is used to store frequently accessed data. When data becomes less frequently accessed it is moved to a cold data storage area on a hard disk drive in the tiered volume. The data exchange is performed on a one-to-one basis reducing the amount and use of DRAM.
    Type: Application
    Filed: February 8, 2011
    Publication date: May 10, 2012
    Inventor: Mark Ish
  • Publication number: 20120117324
    Abstract: A method of virtual cache window headers for long term access history is disclosed. The method may include steps (A) to (C). Step (A) may receive a request at a circuit from a host to access an address in a memory. The circuit generally controls the memory and a cache. Step (B) may update the access history in a first of the headers in response to the request. The headers may divide an address space of the memory into a plurality of windows. Each window generally includes a plurality of subwindows. Each subwindow may be sized to match one of a plurality of cache lines in the cache. A first of the subwindows in a first of the windows may correspond to the address. Step (C) may copy data from the memory to the cache in response to the access history.
    Type: Application
    Filed: August 23, 2011
    Publication date: May 10, 2012
    Inventors: David H. Solina II, Mark Ish
  • Publication number: 20120117328
    Abstract: A method for caching data in a storage medium implementing tiered data structures may include storing a first portion of critical data at the instruction of a storage control module. The first portion of critical data may be separated into data having different priority levels based upon at least one data utilization characteristic associated with a file system implemented by the storage control module. The method may also include storing a second portion of data at the instruction of the storage control module. The second storage medium may have at least one performance, reliability, or security characteristic different from the first storage medium.
    Type: Application
    Filed: November 4, 2010
    Publication date: May 10, 2012
    Applicant: LSI CORPORATION
    Inventors: Brian McKean, Mark Ish
  • Publication number: 20120117332
    Abstract: A method and apparatus for synchronizing input/output commands is provided. An incoming command mask representing an incoming input/output command associated with a memory region is created. In response to a determination that a pending input/output command associated with the memory region is pending, a bitwise inversion operation is performed on the incoming command mask to form a modified incoming command mask. A bitwise AND operation is performed on the modified incoming command mask and the pending command mask to form a pending command locking mask associated with the pending input/output command. A bitwise OR operation is performed between an existing memory lock for a same type of commands and incoming command bit mask to form a new memory region lock.
    Type: Application
    Filed: November 30, 2010
    Publication date: May 10, 2012
    Applicant: LSI CORPORATION
    Inventor: Mark Ish
  • Publication number: 20100268743
    Abstract: Apparatus and methods for improved tree data structure management in a storage controller. A tree assist circuit coupled with a tree memory is provided for integration in a storage controller. I/O processors of the storage controller transmit requests to the tree assist circuit to create, modify, and access tree data structures stored in the tree memory. In one exemplary embodiment, the tree assist circuit is adapted to manage AVL trees. The tree data structures may be used by the I/O processors of the storage controller to manage region lock requests, cache-line lookup request, and other storage management functions of the controller. The I/O processors of the controller may comprise suitable programmed general-purpose processors and/or fast-path I/O request processor circuits.
    Type: Application
    Filed: April 14, 2010
    Publication date: October 21, 2010
    Inventors: Basavaraj G. Hallyal, Robert L. Sheffield, Mark Ish, David H. Solina, Stephen B. Johnson, Gerald E. Smith
  • Publication number: 20100191907
    Abstract: A system transforms data structures absent the need for a backup copy. The system transforms a first logical store in an initial logical arrangement to a desired logical arrangement where the data structures of the logical arrangements are different. The system uses a select sequence of data operations that moves data from its origin in the initial logical arrangement to a target location in the desired logical arrangement. The system generates and properly locates parity information when so desired. The system executes a subsequent data operation in accordance with an indication that the previous data operation was successful. Each subsequent data operation uses the source location from the previous data operation. A non-volatile memory element holds information concerning a present data operation to enable a rollback operation when a present data operation is unsuccessful.
    Type: Application
    Filed: January 26, 2009
    Publication date: July 29, 2010
    Applicant: LSI Corporation
    Inventor: Mark Ish
  • Patent number: 7464125
    Abstract: File system coherency of a file system, particularly for system blocks, may be maintained by (i) duplicating and verifying the (system) blocks, (ii) writing (system) blocks as a sequence of atomic commands so that at any given time, there is a valid (system) block on a physical storage device, and/or (iii) defining the file system directory data structure with directory blocks, each of the directory blocks having at least one of a directory entry and a pointer, where updates to the directory data structure are performed atomically.
    Type: Grant
    Filed: June 14, 2005
    Date of Patent: December 9, 2008
    Assignee: IBRIX Inc.
    Inventors: Steven Alan Orszag, Philip Eric Jackson, Mark Ish
  • Patent number: 5778430
    Abstract: A computer disk cache management method and apparatus which employs a least-recently-used with aging method to determine a best candidate for replacement as a result of a cache miss. A hash function takes as its input a block number and outputs a hash index into a hash table of pointers. Each pointer in the hash table points to a doubly-linked list of headers, with each header having a bit map wherein the bits contained in the map identify whether a particular block of data is contained within the cache. An ordered binary tree (heap) identifies candidates for replacement such that the best candidate for replacement is located at the root of the heap. After every access to a cache line, the heap is locally reorganized based upon a frequency of use and an age of the cache line, such that the least-frequently-used and/or oldest cache line is at the root of the heap.
    Type: Grant
    Filed: April 19, 1996
    Date of Patent: July 7, 1998
    Assignee: ECCS, Inc.
    Inventors: Mark Ish, Federico Giovannetti