Patents by Inventor Mark J. Kilgard

Mark J. Kilgard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10083514
    Abstract: One embodiment of the present invention includes techniques for rasterizing primitives that include edges shared between paths. For each edge, a rasterizer unit selects and applies a sample rule from multiple sample rules. If the edge is shared, then the selected sample rule causes each group of coverage samples associated with a single color sample to be considered as either fully inside or fully outside the edge. Consequently, conflation artifacts caused when the number of coverage samples per pixel exceeds the number of color samples per pixel may be reduced. In prior-art techniques, reducing such conflation artifacts typically involves increasing the number of color samples per pixel to equal the number of coverage samples per pixel. Advantageously, the disclosed techniques enable rendering using algorithms that reduce the ratio of color to coverage samples, thereby decreasing memory consumption and memory bandwidth use, without causing conflation artifacts associated with shared edges.
    Type: Grant
    Filed: October 10, 2016
    Date of Patent: September 25, 2018
    Assignee: NVIDIA CORPORATION
    Inventors: Mark J. Kilgard, Jeffrey A. Bolz
  • Patent number: 9916674
    Abstract: One embodiment of the present invention sets forth a technique for improving path rendering on computer systems with an available graphics processing unit. The technique involves reducing complex path objects to simpler geometric objects suitable for rendering on a graphics processing unit. The process involves a central processing unit “baking” a set of complex path rendering objects to generate a set of simpler graphics objects. A graphics processing unit then renders the simpler graphics objects. This division of processing load can advantageously yield higher overall rendering performance.
    Type: Grant
    Filed: May 19, 2011
    Date of Patent: March 13, 2018
    Assignee: NVIDIA Corporation
    Inventor: Mark J. Kilgard
  • Patent number: 9773341
    Abstract: One embodiment of the present invention includes techniques for rasterizing geometries. First, a processing unit defines a bounding primitive that covers the geometry and does not include any internal edges. If the bounding primitive intersects any enabled clip plane, then the processing unit generates fragments to fill a current viewport. Alternatively, the processing unit generates fragments to fill the bounding primitive. Because the rasterized region includes no internal edges, conflation artifacts caused when the number of coverage samples per pixel exceeds the number of color samples per pixel may be reduced. In prior-art techniques, reducing such conflation artifacts typically involves increasing the number of color samples per pixel to equal the number of coverage samples per pixel.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: September 26, 2017
    Assignee: NVIDIA Corporation
    Inventors: Jeffrey A. Bolz, Mark J. Kilgard
  • Patent number: 9767600
    Abstract: A graphics processing pipeline within a parallel processing unit (PPU) is configured to perform path rendering by generating a collection of graphics primitives that represent each path to be rendered. The graphics processing pipeline determines the coverage of each primitive at a number of stencil sample locations within each different pixel. Then, the graphics processing pipeline reduces the number of stencil samples down to a smaller number of color samples, for each pixel. The graphics processing pipeline is configured to modulate a given color sample associated with a given pixel based on the color values of any graphics primitives that cover the stencil samples from which the color sample was reduced. The final color of the pixel is determined by downsampling the color samples associated with the pixel.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: September 19, 2017
    Assignee: NVIDIA Corporation
    Inventors: Jeffrey A. Bolz, Mark J. Kilgard, Henry Packard Moreton, Rui M. Bastos, Eric B. Lum
  • Patent number: 9613451
    Abstract: One embodiment of the present invention sets forth a technique for rendering anti-aliased paths by first generating an alpha buffer representing coverage data. To generate the alpha buffer, jittered versions of the rendered path are rendered and corresponding stencil buffers indicating sub-pixel samples of the path that should be covered are generated. After each stencil buffer is generated, the jittered path is rasterized to convert the sub-pixel coverage into coverage weights that are stored in the alpha component of a frame buffer. As each jittered path is rasterized, the coverage weights are accumulated. Finally, geometry representing the union of the jittered versions of the path is rendered to shade pixels based on the accumulated coverage weights. The anti-aliased rendered paths may be filled or stroked without tessellating the paths.
    Type: Grant
    Filed: May 17, 2011
    Date of Patent: April 4, 2017
    Assignee: NVIDIA Corporation
    Inventor: Mark J. Kilgard
  • Patent number: 9558573
    Abstract: A technique for efficiently rendering path images tessellates path contours into triangle tans comprising a set of representative triangles. Topology of the set of representative triangles is then optimized for greater rasterization efficiency by applying a flip operator to selected triangle pairs within the set of representative triangles. The optimized triangle pairs are then rendered using a path rendering technique, such as stencil and cover.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: January 31, 2017
    Assignee: NVIDIA Corporation
    Inventors: Jeffrey A. Bolz, Mark J. Kilgard
  • Publication number: 20170024897
    Abstract: One embodiment of the present invention includes techniques for rasterizing primitives that include edges shared between paths. For each edge, a rasterizer unit selects and applies a sample rule from multiple sample rules. If the edge is shared, then the selected sample rule causes each group of coverage samples associated with a single color sample to be considered as either fully inside or fully outside the edge. Consequently, conflation artifacts caused when the number of coverage samples per pixel exceeds the number of color samples per pixel may be reduced. In prior-art techniques, reducing such conflation artifacts typically involves increasing the number of color samples per pixel to equal the number of coverage samples per pixel. Advantageously, the disclosed techniques enable rendering using algorithms that reduce the ratio of color to coverage samples, thereby decreasing memory consumption and memory bandwidth use, without causing conflation artifacts associated with shared edges.
    Type: Application
    Filed: October 10, 2016
    Publication date: January 26, 2017
    Inventors: Mark J. KILGARD, Jeffrey A. BOLZ
  • Patent number: 9466115
    Abstract: One embodiment of the present invention includes techniques for rasterizing primitives that include edges shared between paths. For each edge, a rasterizer unit selects and applies a sample rule from multiple sample rules. If the edge is shared, then the selected sample rule causes each group of coverage samples associated with a single color sample to be considered as either fully inside or fully outside the edge. Consequently, conflation artifacts caused when the number of coverage samples per pixel exceeds the number of color samples per pixel may be reduced. In prior-art techniques, reducing such conflation artifacts typically involves increasing the number of color samples per pixel to equal the number of coverage samples per pixel. Advantageously, the disclosed techniques enable rendering using algorithms that reduce the ratio of color to coverage samples, thereby decreasing memory consumption and memory bandwidth use, without causing conflation artifacts associated with shared edges.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: October 11, 2016
    Assignee: NVIDIA Corporation
    Inventors: Mark J. Kilgard, Jeffrey A. Bolz
  • Patent number: 9418437
    Abstract: One embodiment of the present invention includes techniques for rasterizing primitives that include edges shared between paths. For each edge, a rasterizer unit selects and applies a sample rule from multiple sample rules. If the edge is shared, then the selected sample rule causes each group of coverage samples associated with a single color sample to be considered as either fully inside or fully outside the edge. Consequently, conflation artifacts caused when the number of coverage samples per pixel exceeds the number of color samples per pixel may be reduced. In prior-art techniques, reducing such conflation artifacts typically involves increasing the number of color samples per pixel to equal the number of coverage samples per pixel. Advantageously, the disclosed techniques enable rendering using algorithms that reduce the ratio of color to coverage samples, thereby decreasing memory consumption and memory bandwidth use, without causing conflation artifacts associated with shared edges.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: August 16, 2016
    Assignee: NVIDIA CORPORATION
    Inventors: Mark J. Kilgard, Jeffrey A. Bolz
  • Patent number: 9342891
    Abstract: One embodiment of the present invention includes techniques for rasterizing primitives that include edges shared between paths. For each edge, a rasterizer unit selects and applies a sample rule from multiple sample rules. If the edge is shared, then the selected sample rule causes each group of coverage samples associated with a single color sample to be considered as either fully inside or fully outside the edge. Consequently, conflation artifacts caused when the number of coverage samples per pixel exceeds the number of color samples per pixel may be reduced. In prior-art techniques, reducing such conflation artifacts typically involves increasing the number of color samples per pixel to equal the number of coverage samples per pixel. Advantageously, the disclosed techniques enable rendering using algorithms that reduce the ratio of color to coverage samples, thereby decreasing memory consumption and memory bandwidth use, without causing conflation artifacts associated with shared edges.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: May 17, 2016
    Assignee: NVIDIA Corporation
    Inventors: Mark J. Kilgard, Jeffrey A. Bolz
  • Patent number: 9317960
    Abstract: One embodiment of the present invention sets forth a technique for rendering paths by first generating a stencil buffer indicating pixels of the path that should be covered and then covering the path. The paths may be filled or stroked without tessellating the paths. Path rendering may be accelerated when a graphics processing unit or other processor that is configured to perform operations to generate the stencil buffer and cover the path to fill or stroke the path. When the paths are rendered in a top-to-bottom (front-to-back) order, an opacity stencil may be generated and used to avoid determining path coverage and shading for pixels that are opaque.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: April 19, 2016
    Assignee: NVIDIA Corporation
    Inventor: Mark J. Kilgard
  • Patent number: 9311738
    Abstract: One embodiment of the present invention sets forth a technique for rendering paths by first generating a stencil buffer indicating pixels of the path that should be covered and then covering the path. The paths may be filled or stroked without tessellating the paths. Path rendering may be accelerated when a graphics processing unit or other processor that is configured to perform operations to generate the stencil buffer and cover the path to fill or stroke the path.
    Type: Grant
    Filed: May 4, 2011
    Date of Patent: April 12, 2016
    Assignee: NVIDIA Corporation
    Inventor: Mark J. Kilgard
  • Patent number: 9218691
    Abstract: One embodiment of the present invention sets forth a technique for specifying scene programs, where the effect of executing a particular scene program is to generate a sequence of graphics commands. The application programming interface is extended to include calls used to specify a high-level scene program. Upon receiving a high-level scene program, the graphics driver generates a machine code scene program. When an application program emits a call to execute one or more machine code scene programs, the graphics driver transmits corresponding scene programs execution commands to the graphics pre-processing unit. For each scene program execution command, the graphics pre-processing unit processes instructions, programmatically reconfigures the graphics pipeline based on the execution of the machine code scene program, and launches one or more parallel threads that execute commands within the graphics pipeline.
    Type: Grant
    Filed: May 22, 2008
    Date of Patent: December 22, 2015
    Assignee: NVIDIA CORPORATION
    Inventors: Jason Sams, Cass W. Everitt, Mark J. Kilgard
  • Patent number: 9202303
    Abstract: One embodiment of the present invention sets forth a technique for compositing a rendered path object into an image buffer. A shader program executing within a graphics processing unit (GPU) performs a stenciling operation for the path object and subsequently performs a texture barrier operation, which invalidates caches configured to store texture and frame buffer data within the GPU. The shader program then performs covering operation for the path object in which the shader renders color samples for the path object and composites the color samples into an image buffer. The shader program binds to the image buffer for access as both a texture map and a writeable image. Stencil values are reset when corresponding pixels are written once per path object, and texture caches are invalidated via the texture barrier operation, which is performed after each covering operation per path object.
    Type: Grant
    Filed: May 20, 2011
    Date of Patent: December 1, 2015
    Assignee: NVIDIA Corporation
    Inventors: Jeffrey A. Bolz, Mark J. Kilgard
  • Patent number: 9183609
    Abstract: A technique for efficiently rendering content reduces each complex blend mode to a series of basic blend operations. The series of basic blend operations are executed within a recirculating pipeline until a final blended value is computed. The recirculating pipeline is positioned within a color raster operations unit of a graphics processing unit for efficient access to image buffer data.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: November 10, 2015
    Assignee: NVIDIA Corporation
    Inventors: Rui Bastos, Mark J. Kilgard, William Craig McKnight, Jerome F. Duluk, Jr., Pierre Souillot, Dale L. Kirkland, Christian Amsinck, Joseph Detmer, Christian Rouet, Don Bittel
  • Patent number: 9183662
    Abstract: One embodiment of the present invention sets forth a technique for specifying scene programs, where the effect of executing a particular scene program is to generate a sequence of graphics commands. The application programming interface is extended to include calls used to specify a high-level scene program. Upon receiving a high-level scene program, the graphics driver generates a machine code scene program. When an application program emits a call to execute one or more machine code scene programs, the graphics driver transmits corresponding scene programs execution commands to the graphics pre-processing unit. For each scene program execution command, the graphics pre-processing unit processes instructions, programmatically reconfigures the graphics pipeline based on the execution of the machine code scene program, and launches one or more parallel threads that execute commands within the graphics pipeline.
    Type: Grant
    Filed: May 22, 2008
    Date of Patent: November 10, 2015
    Assignee: NVIDIA Corporation
    Inventors: Jason Sams, Cass W. Everitt, Mark J. Kilgard
  • Patent number: 9024946
    Abstract: One embodiment of the present invention sets forth a technique for performing a computer-implemented method for tessellating patches. An input block is received that defines a plurality of input patch attributes for each patch as well as instructions for processing each input patch. A plurality of threads is launched to execute the instructions to generate each vertex of a corresponding output patch based on the input patch. Reads of values written during instruction execution are synchronized so threads can read and further process the values of other threads. An output patch is then assembled from the outputs of each of the threads; and emitting the output patch for further processing.
    Type: Grant
    Filed: September 10, 2010
    Date of Patent: May 5, 2015
    Assignee: NVIDIA Corporation
    Inventors: Patrick R. Brown, Christopher T. Dodd, Mark J. Kilgard
  • Publication number: 20140267374
    Abstract: One embodiment of the present invention includes techniques for rasterizing primitives that include edges shared between paths. For each edge, a rasterizer unit selects and applies a sample rule from multiple sample rules. If the edge is shared, then the selected sample rule causes each group of coverage samples associated with a single color sample to be considered as either fully inside or fully outside the edge. Consequently, conflation artifacts caused when the number of coverage samples per pixel exceeds the number of color samples per pixel may be reduced. In prior-art techniques, reducing such conflation artifacts typically involves increasing the number of color samples per pixel to equal the number of coverage samples per pixel. Advantageously, the disclosed techniques enable rendering using algorithms that reduce the ratio of color to coverage samples, thereby decreasing memory consumption and memory bandwidth use, without causing conflation artifacts associated with shared edges.
    Type: Application
    Filed: September 16, 2013
    Publication date: September 18, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Mark J. KILGARD, Jeffrey A. BOLZ
  • Publication number: 20140267366
    Abstract: A graphics processing pipeline within a parallel processing unit (PPU) is configured to perform path rendering by generating a collection of graphics primitives that represent each path to be rendered. The graphics processing pipeline determines the coverage of each primitive at a number of stencil sample locations within each different pixel. Then, the graphics processing pipeline reduces the number of stencil samples down to a smaller number of color samples, for each pixel. The graphics processing pipeline is configured to modulate a given color sample associated with a given pixel based on the color values of any graphics primitives that cover the stencil samples from which the color sample was reduced. The final color of the pixel is determined by downsampling the color samples associated with the pixel.
    Type: Application
    Filed: September 5, 2013
    Publication date: September 18, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Jeffrey A. BOLZ, Mark J. KILGARD, Henry Packard MORETON, Rui M. BASTOS, Eric B. LUM
  • Publication number: 20140267373
    Abstract: One embodiment of the present invention includes techniques for rasterizing primitives that include edges shared between paths. For each edge, a rasterizer unit selects and applies a sample rule from multiple sample rules. If the edge is shared, then the selected sample rule causes each group of coverage samples associated with a single color sample to be considered as either fully inside or fully outside the edge. Consequently, conflation artifacts caused when the number of coverage samples per pixel exceeds the number of color samples per pixel may be reduced. In prior-art techniques, reducing such conflation artifacts typically involves increasing the number of color samples per pixel to equal the number of coverage samples per pixel. Advantageously, the disclosed techniques enable rendering using algorithms that reduce the ratio of color to coverage samples, thereby decreasing memory consumption and memory bandwidth use, without causing conflation artifacts associated with shared edges.
    Type: Application
    Filed: September 16, 2013
    Publication date: September 18, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Mark J. KILGARD, Jeffrey A. BOLZ