Abstract: Systems and methods for performing data array resizing using a graphics processor resize a source data array of any dimensions to produce a destination data array of other dimensions. A pixel shader program may be used to configure the graphics processor to sample and filter the source data array to produce the destination data array. One or more destination data arrays may be mip maps of the source data array. A box filter or other type of filter may be used to produce each destination data array. Each pixel in the destination data array is produced in isolation, i.e., independently, thereby permitting the use of parallel processing to produce each pixel in the destination data array.

Abstract: One embodiment of the invention sets forth a method for storing graphics data in a texture array in a local memory coupled to a graphics processing unit. The method includes the steps of specifying the texture array as a target in the local memory, and loading a first block of texture maps into the texture array, wherein each texture map in the first block has a first resolution and corresponds to a different slice of the texture array. One advantage of the disclosed method is that a complete block of texture images may be loaded into a texture array using a single API call. Thus, compared to prior art systems, where a texture array must be loaded one image for one slice of the array at a time, the disclosed method increases the efficiency of using arrays of texture maps for graphics processing operations.

Abstract: Methods and systems for processing a geometry shader program developed in a high-level shading language are disclosed. Specifically, in one embodiment, after having received the geometry shader program configured to be executed by a first processing unit in a programmable execution environment, the high-level shading language instructions of the geometry shader program is converted into low-level programming language instructions. The low-level programming language instructions are then linked with the low-level programming language instructions of a domain-specific shader program, which is configured to be executed by a second processing unit also residing in the programmable execution environment. The linked instructions of the geometry shader program are directed to the first processing unit, and the linked instructions of the domain-specific shader program are directed to the second processing unit.

Abstract: A system, method and computer program product are provided for programmable vertex processing. Initially, a vertex program is identified including branch labels and instruction sequences with branch commands. The vertex program is then converted to a binary format capable of being executed by a hardware graphics pipeline. The vertex program may then be executed in the binary format utilizing the hardware graphics pipeline for transforming vertices. As an option, the vertex program is initially written in a textual format capable of being read by a human prior to being converted.

Abstract: Systems and methods for dynamically canceling texture fetches may improve texture mapping performance. A shader program compiler inserts condition code writes and condition code comparison operations for shader program instructions that contribute to a texture read instruction and do not need to be executed if certain conditions are met. During execution of the shader program, the inserted condition codes are used to compute a dynamic writemask that indicates if the texture data resulting from the texture read is unnecessary. The dynamic writemask is used to cancel unnecessary texture fetches during execution of the shader program.

Abstract: Systems and methods for avoiding unnecessary uncovered texture fetches may improve texture mapping performance. A shader program compiler performs data-flow analysis to determine if texture fetches may be required for pixels that are not covered by a graphics primitive fragment. A graphics driver then determines which texture maps do not require texels for uncovered neighbor pixels, dependent on texture filter mode information, thereby avoiding unnecessary uncovered texture fetches.

Abstract: A system, method and computer program product are provided for programmable vertex processing. Initially, a vertex program is identified including branch labels and instruction sequences with branch commands. The vertex program is then converted to a binary format capable of being executed by a hardware graphics pipeline. The vertex program may then be executed in the binary format utilizing the hardware graphics pipeline for transforming vertices. As an option, the vertex program is initially written in a textual format capable of being read by a human prior to being converted.

Abstract: A system, method and computer program product are provided for performing depth peeling. In use, a first rendering pass is executed for collecting information relating to a first depth layer. Further, at least one additional rendering pass is executed for collecting additional information relating to at least one additional depth layer. Depth peeling is carried out during the execution of the rendering passes by rendering an object, creating a texture based on the rendered object, and rendering the object again utilizing the texture.

Abstract: A system optimizes two or more stream processing programs based upon the data exchanged between the stream processing programs. The system alternately processes each stream processing program to identify and remove dead program code, thereby improving execution performance. Dead program code is identified by propagating constants received as inputs from other stream processing programs and by analyzing a first stream processing program and determining the outputs of a second stream processing program that are unused by the first stream processing program. The system may perform multiple iterations of this optimization is previous iterations introduce additional constants used as inputs to a stream processing program. Following optimization of the stream processing programs, the optimized stream processing programs are compiled to a format adapted to be executed by a stream processing system.

Abstract: Methods and apparatuses for effectively clearing stencil buffers at high speed using surrogate stencil buffer clearing. A hardware register tracks the number of surrogate clears of the stencil buffer since the last actual clear. Bits are reserved in each stencil register for storing the surrogate clear number that cleared other stencil registers the last time the stencil register held an assigned value. A comparison between the contents of the hardware register and the reserved bits in each stencil register determines if each stencil register should be assigned a cleared value. If the numbers do not match the stencil register is assigned a predetermined surrogate clear value. In some applications the number of reserved bits is fixed, while in other applications the number of reserved bits can be set, either by a designer or by software.

Abstract: A system, method and computer program product are provided for programmable processing of fragment data in a computer hardware graphics pipeline. Initially, fragment data is received in a hardware graphics pipeline. It is then determined whether the hardware graphics pipeline is operating in a programmable mode. If it is determined that the hardware graphics pipeline is operating in the programmable mode, programmable operations are performed on the fragment data in order to generate output. The programmable operations are performed in a manner/sequence specified in a graphics application program interface. If it is determined that the hardware graphics pipeline is not operating in the programmable mode, standard graphics application program interface (API) operations are performed on the fragment data in order to generate output.

Abstract: A system, method and computer program product are provided for two-sided stencil testing during graphics processing. Initially, primitives are received to be processed in a graphics processing pipeline. In use, it is then determined whether the graphics processing pipeline is operating with same-sided stencil testing enabled. If same-sided stencil testing is not enabled, the primitives are passed without same-sided stencil testing and two-sided stencil testing. If, on other hand, same-sided stencil testing is enabled, it is determined whether the graphics processing pipeline is operating with two-sided stencil testing enabled. If the two-sided stencil testing is enabled and the same-sided stencil testing is enabled, two-sided stencil testing is performed on the primitives. If, on the other hand, the two-sided stencil testing is disabled and the same-sided stencil testing is enabled, same-sided stencil testing is performed on the primitives.

Abstract: A system and method for interfacing graphics program modules written to execute on a plurality of functional units of a graphics processor using a shared memory. A central processing unit (CPU) receives a first graphics program module that outputs a first parameter referenced by a first graphics program module identifier, a second graphics program module that inputs the first parameter by referencing the first graphics program module identifier, and a first data structure that includes, in a pre-defined order, a list of first data structure identifiers. The CPU identifies a memory location in the shared memory, based on the pre-defined order of the first data structure identifiers, for one of the first data structure identifiers that is the same as the first graphics program module identifier. The CPU modifies the first and second graphics program modules to reference the first parameter by the identified memory location in the shared memory.

Abstract: A system, method and computer program product are provided for depth clamping in a hardware graphics pipeline. Initially, a depth value is identified. It is then determined as to whether a hardware graphics pipeline is operating in a depth clamping mode. If the hardware graphics pipeline is operating in the depth clamping mode, the depth value is clamped within a predetermined range utilizing the hardware graphics pipeline.

Abstract: A system and method are provided for conditional branching in a hardware graphics pipeline. Initially, a plurality of graphics commands is received. Condition data is then affected based on at least some of the graphics commands utilizing the hardware graphics pipeline. At least one of the graphics commands is then conditionally skipping based on the condition data in response to another graphics command utilizing the hardware graphics pipeline.

Abstract: A central processing unit (CPU) including an operating system for executing code segments capable of performing graphics processing on the CPU. Associated therewith is a graphics application specific integrated circuit (ASIC) for performing graphics processing in accordance with a graphics processing standard. An extension to the software is included that identifies a first portion of the graphics processing to be performed on the graphics ASIC and a second portion of the graphics processing to be performed on the CPU. Such second portion of the graphics processing includes application-programmable vertex processing unavailable by the graphics ASIC. A compiler compiles the software to execute the first portion of the graphics processing on the graphics ASIC and the second portion of the graphics processing on the CPU in accordance with the extension.

Abstract: Lights can be conservatively bounded within a depth range. When image pixels are outside of a light's depth range, an associated volume fragment does not have to be rendered. Depth bounds registers can be used to store minimum and maximum depth values for a light. As graphics hardware processes volume fragments overlapping the image, the image's depth values are compared with the values in the depth bounds register. If the image's depth is outside of the depth range for the light, stencil buffer and illumination operations for this volume fragment are bypassed. This optimization can be performed on a per-pixel basis, or simultaneously on a group of adjacent pixels. The depth bounds are calculated from the light, or from the intersection of the volume with one or more other features. A rendering application uses API functions to set the depth bounds for each light and to activate depth bounds checking.

Abstract: A system, method and computer program product are provided for buffering data in a computer graphics pipeline. Initially, graphics floating point data is read from a buffer in a graphics pipeline. Next, the graphics floating point data is operated upon in the graphics pipeline. Further, the graphics floating point data is stored to the buffer in the graphics pipeline.

Abstract: A system, method and computer program product are provided for branching during programmable processing utilizing a graphics application program interface in conjunction with a hardware graphics pipeline. Initially, a first instruction defined by the graphics application program interface is identified. A first operation is performed on graphics data based on the first instruction utilizing the hardware graphics pipeline. Any some point, the present technique may involve branching to an additional instruction defined by the graphics application program interface other than a subsequent sequential instruction. Next, another operation is performed on the graphics data based on the additional instruction utilizing the hardware graphics pipeline.

Abstract: A system, method and computer program product are provided for transparency rendering in a graphics pipeline. Initially, colored-transparency information is collected from a plurality of depth layers (i.e. colored-transparency layers, etc.) in a scene to be rendered. The collected colored-transparency information is then stored in memory. The colored-transparency information from the depth layers may then be blended in a predetermined order.