Abstract: A system, method and computer program product are provided for programmable processing of fragment data in a computer hardware graphics pipeline. Initially, fragment data is received in a hardware graphics pipeline. It is then determined whether the hardware graphics pipeline is operating in a programmable mode. If it is determined that the hardware graphics pipeline is operating in the programmable mode, programmable operations are performed on the fragment data in order to generate output. The programmable operations are performed in a manner/sequence specified in a graphics application program interface. If it is determined that the hardware graphics pipeline is not operating in the programmable mode, standard graphics application program interface (API) operations are performed on the fragment data in order to generate output.

Abstract: A method and system for synchronizing updates of vertex data by a processor with a graphics accelerator module that is fetching vertex data is disclosed. The method and system comprises providing vertex array range (VAR) and writing vertex data into the VAR. The method and system includes providing a command into a command stream of the graphics accelerator module indicating that the vertex data has written into the VAR, and providing a fence condition based upon the command. A system and method in accordance with the present invention thus permits extremely high vertex processing rates via vertex arrays or vertex buffers even when the processor lacks the necessary data movement bandwidth. By passing indices in lieu of the vertex data, the processor is capable of keeping up with the rate at which a vertex engine of the graphics accelerator module can consume vertices.

Abstract: A system, method and article of manufacture are provided for aliasing vertex attributes during vertex processing. Initially, a plurality of identifiers are each mapped to one of a plurality of parameters associated with vertex data. Thereafter, the vertex data is processed by calling the parameters utilizing a vertex program capable of referencing the parameters using the identifiers.

Abstract: An invention is provided for rendering using an omnidirectional light. A shadow cube texture map having six cube faces centered by a light source is generated. Each cube face comprises a shadow texture having depth data from a perspective of the light source. In addition, each cube face is associated with an axis of a three-dimensional coordinate system. For each object fragment rendered from the camera's perspective a light-to-surface vector is defined from the light source to the object fragment, and particular texels within particular cube faces are selected based on the light-to-surface vector. The texel values are tested against a depth value computed from the light to surface vector. The object fragment is textured as in light or shadow according to the outcome of the test.

Abstract: A system, method, and article of manufacture are provided for allowing direct memory access to graphics vertex data by a graphics accelerator module. First, vertex data is stored in memory. Next, an index is received which is representative of a portion of the vertex data in the memory. A location is then determined in the memory in which the portion of the vertex data is stored. Such portion of the vertex data may thereafter be directly retrieved from the determined location in the memory while bypassing a processor.

Abstract: Lights can be conservatively bounded within a depth range. When image pixels are outside of a light's depth range, an associated volume fragment does not have to be rendered. Depth bounds registers can be used to store minimum and maximum depth values for a light. As graphics hardware processes volume fragments overlapping the image, the image's depth values are compared with the values in the depth bounds register. If the image's depth is outside of the depth range for the light, stencil buffer and illumination operations for this volume fragment are bypassed. This optimization can be performed on a per-pixel basis, or simultaneously on a group of adjacent pixels. The depth bounds are calculated from the light, or from the intersection of the volume with one or more other features. A rendering application uses API functions to set the depth bounds for each light and to activate depth bounds checking.

Abstract: A system, method and computer program product are provided for two-sided stencil testing during graphics processing. Initially, primitives are received to be processed in a graphics processing pipeline. In use, it is then determined whether the graphics processing pipeline is operating with same-sided stencil testing enabled. If same-sided stencil testing is not enabled, the primitives are passed without same-sided stencil testing and two-sided stencil testing. If, on other hand, same-sided stencil testing is enabled, it is determined whether the graphics processing pipeline is operating with two-sided stencil testing enabled. If the two-sided stencil testing is enabled and the same-sided stencil testing is enabled, two-sided stencil testing is performed on the primitives. If, on the other hand, the two-sided stencil testing is disabled and the same-sided stencil testing is enabled, same-sided stencil testing is performed on the primitives.

Abstract: A system, method and computer program product are provided for depth clamping in a hardware graphics pipeline. Initially, a depth value is identified. It is then determined as to whether a hardware graphics pipeline is operating in a depth clamping mode. If the hardware graphics pipeline is operating in the depth clamping mode, the depth value is clamped within a predetermined range utilizing the hardware graphics pipeline.

Abstract: A system and method are provided for using information from at least one depth layer and for collecting information about at least one additional depth layer utilizing a graphics pipeline. Initially, constraining depth layers are provided which, in turn, define a plurality of depth constraints. Next, a plurality of tests is performed involving the constraining depth layers for collecting information about at least one additional depth layer. The information relating to the at least one depth layer may then be used to improve processing in the graphics pipeline. By the foregoing multiple tests, information relating to a plurality of depth layers may be collected during each of a plurality of rendering passes. Initially, information relating to the constraining depth layers and associated depth constraints is provided in the aforementioned manner. Thereafter, information relating to at least one additional depth layer is collected during additional rendering passes using multiple tests on each rendering pass.

Abstract: A system, method and computer program product are provided for programmable processing of fragment data in a computer hardware graphics pipeline. Initially, fragment data is received in a hardware graphics pipeline. It is then determined whether the hardware graphics pipeline is operating in a programmable mode. If it is determined that the hardware graphics pipeline is operating in the programmable mode, programmable operations are performed on the fragment data in order to generate output. The programmable operations are performed in a manner/sequence specified in a graphics application program interface. If it is determined that the hardware graphics pipeline is not operating in the programmable mode, standard graphics application program interface (API) operations are performed on the fragment data in order to generate output.

Abstract: A system and method are provided for improved shadow mapping in a graphics pipeline. Raw depth values are initially collected from two depth layers in a scene to be rendered. Shadow-map depth values are then calculated utilizing the raw depth values. The scene is then shadow mapped utilizing the shadow-map depth values in order to improve the appearance of shadows in a rendered scene. The various steps are carried out by a hardware-implemented graphics pipeline, which may include texturing or shadowing mapping hardware.

Abstract: A system, method and computer program product are provided for tracking a matrix during vertex processing. Initially, a request is received to track a matrix. Such matrix is identified in the request. The identified matrix is then tracked for vertex processing. In one aspect of the present embodiment, a version, type, and/or name of the matrix is identified in the request.

Abstract: A system is provided for improving performance during graphics processing that involves application-programmable vertex processing. First included is a central processing unit (CPU) including an operating system for executing code segments capable of performing graphics processing on the CPU. Associated therewith is a graphics application specific integrated circuit (ASIC) including a hardware-implemented graphics pipeline capable of performing graphics processing in accordance with a graphics processing standard. Also provided is software written in accordance with the graphics processing standard. Such software is adapted for directing the graphics ASIC to perform the graphics processing. An extension to the software is included that identifies a first portion of the graphics processing to be performed on the graphics ASIC and a second portion of the graphics processing to be performed on the CPU.

Abstract: A method and system for synchronizing updates of vertex data by a processor with a graphics accelerator module that is fetching vertex data is disclosed. The method and system comprises providing vertex array range (VAR) and writing vertex data into the VAR. The method and system includes providing a command into a command stream of the graphics accelerator module indicating that the vertex data has written into the VAR, and providing a fence condition based upon the command. A system and method in accordance with the present invention thus permits extremely high vertex processing rates via vertex arrays or vertex buffers even when the processor lacks the necessary data movement bandwidth. By passing indices in lieu of the vertex data, the processor is capable of keeping up with the rate at which a vertex engine of the graphics accelerator module can consume vertices.