Abstract: A variable length connecting rod (12) has a first locking mechanism (36) for releasably locking connecting rod parts in a first effective length setting (FIG. 7) for the rod, and a second locking mechanism (38) for releasably locking the connecting rod parts in a second effective length setting to change the compression ratio for an engine cylinder. When a length change is to be made, hydraulic fluid unlocks a locked one of the locking mechanisms, allowing inertial force to effect the length change during an engine cycle. At completion of a length change, the other locking mechanism automatically unlocks.

Abstract: A variable length connecting rod assembly for imparting a variable compression ratio to an internal combustion engine. The assembly contains a first part (22; 72), a second part (20; 74), and a third part (34; 70) assembled together to form the large end of the connecting rod assembly and provide a variable length for the connecting rod assembly. The first part is a semi-circular cap. One (20; 74) of the second and third parts is fastened tight to the first part (22; 72). Guides (36, 38, 48; 88, 90, 92) disposed at opposite sides of the large end operatively relate the other (34; 70) of the second and third parts and the fastened parts to provide for relative sliding motion between the other of the second and third parts and the fastened parts over a limited adjustment range to change the length of the connecting rod assembly.

Abstract: Methods of fabricating source/drain regions and transistors incorporating the same are provided. In one aspect, a method of fabricating a source/drain region in a substrate is provided that includes forming a stack on the substrate with a gate electrode and an insulating layer positioned on the gate electrode that has etch selectivity to the gate electrode. A first doped region is formed in the substrate adjacent to the stack with a first horizontal junction. A second doped region is formed in the substrate that overlaps the first doped region and has a second horizontal junction positioned beneath the first horizontal junction. An implant of impurity ions into the substrate is performed to establish a third doped region that overlaps the second doped region and has a third horizontal junction positioned beneath the second horizontal junction. The insulating layer prevents impurity ions from substantially penetrating through the gate electrode.

Abstract: Integrated circuits with transistors exhibiting improved junction capacitances and various methods of fabricating the same are provided. In one aspect, a method of manufacturing is provided that includes forming a doped region in an active area of a substrate wherein the doped region has a first conductivity type and a first horizontal junction. A first source/drain region of the first conductivity type is formed in the active area with a second horizontal junction. A second source/drain region of the first conductivity type is formed in the active area with a third horizontal junction and a lateral separation from the first source/drain region that defines a channel region. The second and third horizontal junctions are positioned substantially at the first horizontal junction. The portion of the doped region positioned in the channel region is doped with an impurity of a second conductivity type that is opposite to the first conductivity type.

Abstract: Characterization of plasma-induced damage in semiconductor manufacturing has long been considered unimportant because the damage had no discernable effect on circuit performance. With increasing transistor counts on an integrated circuit, the damage-induced parasitics are becoming increasingly important. Electrical characterization of such effects provides a far more sensitive method for determining the extent of damage and the effectiveness of efforts to repair the damage. A measurement of diode leakage current through a plasma-etch effect test diode which is formed completely within an active device region, removed from field oxide regions quantifies the extent of damage created by a plasma and the effectiveness of a repair technique that may be applied to the process.

Abstract: Characterization of plasma-induced damage in semiconductor manufacturing has long been considered unimportant because the damage had no discernible effect on circuit performance. With increasing transistor counts on an integrated circuit, the damage-induced parasitics are becoming increasingly important. Electrical characterization of such effects provides a far more sensitive method for determining the extent of damage and the effectiveness of efforts to repair the damage. A measurement of diode leakage current through a plasma-etch effect test diode which is formed completely within an active device region, removed from field oxide regions quantifies the extent of damage created by a plasma and the effectiveness of a repair technique that may be applied to the process.

Abstract: A deadbolt locking actuator includes a housing mounting a reversible motor. A worm is fitted on an output shaft of the motor and meshed with a worm gear. A rotary arm is provided outside of the housing and coupled to the worm gear. A pin on the rotary arm is received in an elongated slot of a link connected to a manual locking lever of a door latch. A control circuit operates the drive unit and link between deadbolt and non-deadbolt positions.

Abstract: The present invention relates to mutants of the green fluorescent protein having improved fluorescent properties at 37.degree. C. The mutants provide for improved methods of monitoring gene expression, e.g., for use as cell markers or protein expression indicators in prokaryotic and, especially, eucaryotic systems where the standard physiological temperature is 37.degree. C.

Abstract: A process and system for transferring data including at least one slave device connected to at least one master device through an arbiter device. The master and slave devices are connected by a single address bus, a write data bus and a read data bus. The arbiter device receives requests for data transfers from the master devices and selectively transmits the requests to the slave devices. The master devices and the slave devices are further connected by a plurality of transfer qualifier signals which may specify predetermined characteristics of the requested data transfers. Control signals are also communicated between the arbiter device and the slave devices to allow appropriate slave devices to latch addresses of requested second transfers during the pendency of current or primary data transfers so as to obviate an address transfer latency typically required for the second transfer.

Abstract: A composite elastic material includes a layer of ribbon-shaped elastomeric elements disposed in machine direction alignment and point bonded to an extensible layer which may be a gatherable layer or a stretchable layer. A layer of meltblown elastomeric fibers may be bonded to the layer of elastomeric ribbon-shaped elements before bonding to the extensible layer. The elastic composite has excellent cohesion, controlled breathability to air and water vapor, an opaque appearance, and is easy to cut and convert to end use products such as garments, pads, diapers, and personal care products where elasticity is desired.

Abstract: A method and implementing system are provided which includes a DMA controller coupled to a slave bus controller through a processor local bus. The slave bus controller is also coupled to a memory unit. The memory unit is connected directly to a peripheral device. The DMA controller is arranged to receive a data transfer request from the peripheral unit and initiate a transfer cycle with the slave bus controller. The slave bus controller is selectively operable to assert a transfer signal to the memory unit which enables data movement directly between memory and the peripheral device in accordance with the request from the peripheral device. Upon completion of the address transfer and prior to the completion of the data transfer, the slave bus controller generates a transfer complete signal back to the peripheral device. This technique allows for a DMA FlyBy transfer to be overlapped with a subsequent processor local bus transfer.

Abstract: The present invention provides a method and system for fixed length bursts of data on a bus within a data processing system. The method and system in accordance with the present invention provides a burst transfer protocol which includes the providing of length information of a fixed length burst of data on a signal from at least one master device to at least one slave device when the at least one master device requests the fixed length burst of data. It also includes the asserting of a burst termination signal by the at least one slave device one cycle prior to a last cycle in the fixed length burst, and the asserting of a burst complete signal during the last cycle in the fixed length burst for a write burst, or one cycle prior to the last cycle in the fixed length burst for a read burst, based on the value of the signal. This burst transfer protocol enables burst transfers of a maximum length to be performed across a local bus between a master and a slave without dead cycle penalties after the transfer.

Abstract: A DMA Controller, in response to a data transfer request from a slave device, initiates a memory transfer cycle and informs the slave device when the data transfer has completed. In order to avoid dead clock cycles on internal bus(es), the DMA Controller initiates a speculative data transfer cycle after the notification. The DMA Controller aborts the speculative data transfer cycle if the slave device does not request another data transfer within a predetermined time.

Abstract: The invention relates to a catalyst for conversion of methanol, ethanol alone or in combination with n-propanol to isobutanol and the process for making and using the catalyst. The catalyst is a noble metal supported on at least a first phase of mixed oxide crystallites containing from about 60 to about 74 atomic % (on a metals basis only) zirconium, from about 21 to about 31 atomic % manganese and from about 5 to about 9 atomic % zinc, and less than about 1 atomic % alkali, a second phase of zirconium-doped hetaerolite particles containing from about 65 to about 69 atomic % manganese, from about 31 to about 35 atomic % zinc, from about 0.5 to about 5 atomic % zirconium, and optionally a trace atomic % of alkali, and a third phase containing from about 29 to about 55 atomic % manganese, from about 13 to about 55 atomic % zinc and from about 13 to about 35 atomic % zirconium. The first phase mixed oxide crystallites have a zirconium oxide-like structure have a particle size of at least about 40 .ANG.

Abstract: A method and apparatus is provided which allows overlapping of DMA line read and line write cycles. In an exemplary embodiment, the PLB Line Read Word Address bus is used with a DMA controller sideband signal to detect the conditions required to allow the DMA controller to start the line write one cycle prior to the completion of the line read cycle. A reference bit is set when the first word of a multi-word line transfer has been read. A sideband timing signal is generated one cycle prior to the completion of the read cycle indicating that there is only one read data phase remaining of the line read. If the first word to be written out to memory has been read or is available when the timing signal is generated, the write operation is begun prior to the final phase of the memory read transfer, and the read and write operations are overlapped thereby accomplishing an overlapped read/write transfer in fewer cycles than the sum of read and write transfer cycles if done sequentially.

Abstract: The invention relates to a catalyst for conversion of methanol, ethanol alone or in combination with n-propanol to isobutanol and the process for making and using the catalyst. The catalyst is a noble metal supported on at least a first phase of mixed oxide crystallites containing from about 60 to about 74 atomic % (on a metals basis only) zirconium, from about 21 to about 31 atomic % manganese and from about 5 to about 9 atomic % zinc, and less than about 1 atomic % alkali, a second phase of zirconium-doped hetaerolite particles containing from about 65 to about 69 atomic % manganese, from about 31 to about 35 atomic % zinc, from about 0.5 to about 5 atomic % zirconium, and optionally a trace atomic % of alkali, and a third phase containing from about 29 to about 55 atomic % manganese, from about 13 to about 55 atomic % zinc and from about 13 to about 35 atomic % zirconium. The first phase mixed oxide crystallites have a zirconium oxide-like structure have a particle size of at least about 40 .ANG.

Abstract: A reciprocating internal combustion engine includes a siamesed piston bore having a configuration formed by the intersection of two circular cylindrical elements and a matching piston having a similar siamesed configuration. This cylinder configuration allows a four cylinder engine to be about 25% shorter with the same displacement as an engine having circular cylinders and the same stroke.

Abstract: A communication system and method of communicating including a slave function connected to a master function by a single address bus, a write data bus and a read data bus so as to allow for overlapping multiple cycle read and write operations between the master function and the slave function. Preferably the communication system includes a plurality of slave functions connected to a master function by the single address bus, the write data bus and the read data bus. A plurality of master functions may be connected to the slave functions through a bus arbiter connected to the plurality of master functions by an address bus, a write data bus and a read data bus for each master function. The bus arbiter receives requests for communication operations from the plurality of master functions and selectively transmits the communication operations to the slave functions.

Abstract: A dynamically configured memory controller to prevent speculative memory accesses of non-well behaved memory. Such dynamic configuration of a memory controller may be accomplished by providing to the memory controller guard information associated with memory requests. The memory controller may then prevent speculative memory accesses when the guard information indicates that the memory requests are of non-well behaved memory. The guard information provided to the memory controller may include guard information associated with each memory request provided to the memory controller.