Patents by Inventor Mark Pavier

Mark Pavier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250079330
    Abstract: An embedded chip-package is provided. In one example, the embedded chip-package includes a chip, an electrically insulating material at least partially encapsulating the chip, at least one metal layer configured to provide at least one electrically conductive connection to the chip, and an information section. The information section includes coded information about the embedded chip-package, wherein, in the information section, the information is coded as a pattern of electrically conductive portions and electrically insulating portions.
    Type: Application
    Filed: August 15, 2024
    Publication date: March 6, 2025
    Applicant: Infineon Technologies AG
    Inventors: Mahadi-Ul HASSAN, Mark PAVIER
  • Publication number: 20240413094
    Abstract: One or more structures and/or methods are provided. In an example of the subject matter presented herein, an apparatus includes a circuit board substrate. A package comprising a semiconductor die and a redistribution layer over the semiconductor die is mounted to the circuit board substrate. A first component is mounted to the redistribution layer over the semiconductor die. A shielding structure is mounted to the circuit board substrate over the package and the first component.
    Type: Application
    Filed: June 6, 2023
    Publication date: December 12, 2024
    Inventors: Thorsten MEYER, Ludwig HEITZER, Clive O'DELL, Mark PAVIER, Paul WESTMARLAND
  • Publication number: 20240404983
    Abstract: A method for fabricating a semiconductor device includes: providing a carrier; providing first and second external contacts; providing a semiconductor die including a first main face, a second main face opposite to the first main face, a first contact pad disposed on the first main face, a second contact pad disposed on the second main face, and a vertical transistor; disposing the semiconductor die with the first main face onto the carrier; connecting a wire with the second external contact; and connecting a clip between the second contact pad and the first external contact. Connecting the wire is carried out before connecting the clip.
    Type: Application
    Filed: August 12, 2024
    Publication date: December 5, 2024
    Inventor: Mark Pavier
  • Publication number: 20240288363
    Abstract: A package for an optical radiation device comprises a base structure having arranged thereon an optical radiation device, an optically transparent lid element bonded to the base structure defining a cavity between the base structure and the lid element, and a bond structure in a bonding region between the base structure and the lid element, wherein the bond structure is arranged to provide an adhesive bond between the base structure and the lid element, and wherein the bond structure comprises a diffusion layer having a gas diffusive material or gas diffusive structure for providing a gas diffusion path between the cavity and the surrounding atmosphere.
    Type: Application
    Filed: February 20, 2024
    Publication date: August 29, 2024
    Inventors: Christoph Glacer, Ulrich Krumbein, Tobias Mittereder, Mark Pavier, Siyuan Qi, Hugh Richard, David Tumpold, Paul Westmarland
  • Patent number: 12068274
    Abstract: A semiconductor device includes a first carrier, a first external contact, a second external contact, and a first semiconductor die. The first semiconductor die has a first main face, a second main face opposite to the first main face, a first contact pad disposed on the first main face, a second contact pad disposed on the second main face, a third contact pad disposed on the second main face, and a vertical transistor. The first semiconductor die is disposed with the first main face on the first carrier. A clip connects the second contact pad and the second external contact. A first wire is connected with the first external contact. The first wire is disposed at least partially under the clip.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: August 20, 2024
    Assignee: Infineon Technologies AG
    Inventor: Mark Pavier
  • Patent number: 12063474
    Abstract: A sound transducer device includes a multilayer component board having a first side and an opposite second side, and a sound port extending between the first and second sides of the multilayer component board. The sound transducer also includes a MEMS sound transducer die including a suspended membrane structure, wherein the MEMS sound transducer die is arranged at the first side of the multilayer component board such that the suspended membrane structure is in fluid communication with the sound port. The sound transducer also includes a mesh structure for providing an environmental barrier, the mesh structure covering the sound port from either one of the first and second sides of the multilayer component board.
    Type: Grant
    Filed: April 22, 2022
    Date of Patent: August 13, 2024
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Paul Westmarland, Bernd Goller, Scott Palmer, Mark Pavier
  • Patent number: 12057376
    Abstract: An interconnect clip includes a die attach pad that comp includes rises a die attach surface at an inner side of the interconnect clip, a heat dissipation pad that includes a heat dissipation surface at an outer side of the interconnect clip, and a lead contact pad that includes a lead contact surface at an inner side of the interconnect clip or at an outer side of the interconnect clip. The outer side of the interconnect clip in the lead contact pad faces and is spaced apart from the inner side of the interconnect clip in the heat dissipation pad, and the inner side of the interconnect clip in the lead contact pad faces and is spaced apart from the outer side of the interconnect clip in the die attach pad.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: August 6, 2024
    Assignee: Infineon Technologies AG
    Inventors: Azlina Kassim, Thai Kee Gan, Mark Pavier, Ke Yan Tean, Mohd Hasrul Zulkifli
  • Publication number: 20240203836
    Abstract: A semiconductor package includes a substrate, a high voltage semiconductor die attached to an electrically conductive part of the substrate, and a gate driver semiconductor die attached, by an electrically insulative die attach material, to the electrically conductive part of the substrate or to a side of the high voltage semiconductor die that faces away from the substrate. The gate driver semiconductor die includes a semiconductor body and a polymer material covering a backside of the semiconductor body. The polymer material is interposed between the semiconductor body and the die attach material such that the semiconductor body is electrically insulated from the substrate or the side of the high voltage semiconductor die that faces away from the substrate by an insulator stack that includes both the polymer material and the die attach material. A method of producing the semiconductor package also is described.
    Type: Application
    Filed: December 19, 2022
    Publication date: June 20, 2024
    Inventors: Hugh Richard, Mark Pavier
  • Publication number: 20240202485
    Abstract: A wafer-level package sensor device including a capacitive sensor, a controller which is electrically conductively connected to the sensor, wherein the capacitive sensor is formed by partially overlapping redistribution layer tracks of the wafer-level package sensor device formed in different planes, and multiple contact surfaces connected to the controller, which are configured to electrically couple to a chip card module carrier using a flip-chip connection.
    Type: Application
    Filed: November 30, 2023
    Publication date: June 20, 2024
    Inventors: Frank Püschner, Mark Pavier, Bernd Ebersberger
  • Publication number: 20240145402
    Abstract: One or more structures and/or methods are provided. In an example of the subject matter presented herein, an apparatus includes a circuit board, a first component mounted to the circuit board, a shielding structure mounted to the circuit board and having a first platform elevated over the circuit board, and a semiconductor die mounted to the first platform, wherein the shielding structure is between the first component and the semiconductor die.
    Type: Application
    Filed: October 26, 2022
    Publication date: May 2, 2024
    Inventors: Mark PAVIER, Paul WESTMARLAND, Hugh RICHARD
  • Publication number: 20240030502
    Abstract: In an embodiment, a semiconductor device is provided that includes a semiconductor die having a front side, a rear side opposing the front side, and side faces, a first transistor device having a first source pad and a first gate pad on the front side, and a second transistor device having a second source pad and a second gate pad on the front side. The first and second transistor devices each have a drain that is electrically coupled to a common drain pad on the rear side of the semiconductor die. The drain pad has an upper surface and side faces and at least a central portion of the upper surface is covered by a first electrically insulating layer.
    Type: Application
    Filed: June 9, 2023
    Publication date: January 25, 2024
    Inventors: Christian Ranacher, Evelyn Napetschnig, Sandra Ebner, Mark Pavier, Stanislav Vitanov, Paul Frank
  • Patent number: 11609180
    Abstract: The present disclosure concerns an emitter package for a photoacoustic sensor, the emitter package comprising a MEMS infrared radiation source for emitting pulsed infrared radiation in a first wavelength range. The MEMS infrared radiation source may be arranged on a substrate. The emitter package may further comprise a rigid wall structure being arranged on the substrate and laterally surrounding a periphery of the MEMS infrared radiation source. The emitter package may further comprise a lid structure being attached to the rigid wall structure, the lid structure comprising a filter structure for filtering the infrared radiation emitted from the MEMS infrared radiation source and for providing a filtered infrared radiation in a reduced second wavelength range.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: March 21, 2023
    Assignee: Infineon Technologies AG
    Inventors: Siyuan Qi, Joachim Eder, Christoph Glacer, Dominic Maier, Mark Pavier
  • Publication number: 20220369042
    Abstract: A sound transducer device includes a multilayer component board having a first side and an opposite second side, and a sound port extending between the first and second sides of the multilayer component board. The sound transducer also includes a MEMS sound transducer die including a suspended membrane structure, wherein the MEMS sound transducer die is arranged at the first side of the multilayer component board such that the suspended membrane structure is in fluid communication with the sound port. The sound transducer also includes a mesh structure for providing an environmental barrier, the mesh structure covering the sound port from either one of the first and second sides of the multilayer component board.
    Type: Application
    Filed: April 22, 2022
    Publication date: November 17, 2022
    Inventors: Paul Westmarland, Bernd Goller, Scott Palmer, Mark Pavier
  • Patent number: 11393743
    Abstract: A semiconductor device includes a conductive frame comprising a die attach surface that is substantially planar, a semiconductor die comprising a first load on a rear surface and a second terminal disposed on a main surface, a first conductive contact structure disposed on the die attach surface, and a second conductive contact structure on the main surface. The first conductive contact structure vertically extends past a plane of the main surface of the semiconductor die. The first conductive contact structure is electrically isolated from the main surface of the semiconductor die by an electrical isolation structure. An upper surface of the electrical isolation structure is below the main surface of the semiconductor die.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: July 19, 2022
    Assignee: Infineon Technologies AG
    Inventors: Stuart Cardwell, Chee Yang Ng, Josef Maerz, Clive O'Dell, Mark Pavier
  • Publication number: 20220139811
    Abstract: An interconnect clip includes a die attach pad that comp includes rises a die attach surface at an inner side of the interconnect clip, a heat dissipation pad that includes a heat dissipation surface at an outer side of the interconnect clip, and a lead contact pad that includes a lead contact surface at an inner side of the interconnect clip or at an outer side of the interconnect clip. The outer side of the interconnect clip in the lead contact pad faces and is spaced apart from the inner side of the interconnect clip in the heat dissipation pad, and the inner side of the interconnect clip in the lead contact pad faces and is spaced apart from the outer side of the interconnect clip in the die attach pad.
    Type: Application
    Filed: November 2, 2020
    Publication date: May 5, 2022
    Inventors: Azlina Kassim, Thai Kee Gan, Mark Pavier, Ke Yan Tean, Mohd Hasrul Zulkifli
  • Publication number: 20210193560
    Abstract: A semiconductor device includes a conductive frame comprising a die attach surface that is substantially planar, a semiconductor die comprising a first load on a rear surface and a second terminal disposed on a main surface, a first conductive contact structure disposed on the die attach surface, and a second conductive contact structure on the main surface. The first conductive contact structure vertically extends past a plane of the main surface of the semiconductor die. The first conductive contact structure is electrically isolated from the main surface of the semiconductor die by an electrical isolation structure. An upper surface of the electrical isolation structure is below the main surface of the semiconductor die.
    Type: Application
    Filed: December 18, 2019
    Publication date: June 24, 2021
    Inventors: Stuart Cardwell, Chee Yang Ng, Josef Maerz, Clive O'Dell, Mark Pavier
  • Publication number: 20210172862
    Abstract: The present disclosure concerns an emitter package for a photoacoustic sensor, the emitter package comprising a MEMS infrared radiation source for emitting pulsed infrared radiation in a first wavelength range. The MEMS infrared radiation source may be arranged on a substrate. The emitter package may further comprise a rigid wall structure being arranged on the substrate and laterally surrounding a periphery of the MEMS infrared radiation source. The emitter package may further comprise a lid structure being attached to the rigid wall structure, the lid structure comprising a filter structure for filtering the infrared radiation emitted from the MEMS infrared radiation source and for providing a filtered infrared radiation in a reduced second wavelength range.
    Type: Application
    Filed: November 18, 2020
    Publication date: June 10, 2021
    Inventors: Siyuan Qi, Joachim Eder, Christoph Glacer, Dominic Maier, Mark Pavier
  • Publication number: 20210175200
    Abstract: A semiconductor device includes a first carrier, a first external contact, a second external contact, and a first semiconductor die. The first semiconductor die has a first main face, a second main face opposite to the first main face, a first contact pad disposed on the first main face, a second contact pad disposed on the second main face, a third contact pad disposed on the second main face, and a vertical transistor. The first semiconductor die is disposed with the first main face on the first carrier. A clip connects the second contact pad and the second external contact. A first wire is connected with the first external contact. The first wire is disposed at least partially under the clip.
    Type: Application
    Filed: December 3, 2020
    Publication date: June 10, 2021
    Inventor: Mark Pavier
  • Patent number: 10283432
    Abstract: A method of manufacturing a package, wherein the method comprises a forming a chip carrier by covering a thermally conductive and electrically insulating core on both opposing main surfaces thereof at least partially by a respective electrically conductive layer by brazing the respective electrically conductive layer on a respective one of the main surfaces; a mounting at least one electronic chip on the chip carrier; an electrically coupling an electrically conductive contact structure with the at least one electronic chip; and an encapsulating part of the electrically conductive contact structure, and at least part of the chip carrier and of the at least one electronic chip by a mold-type encapsulant.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: May 7, 2019
    Assignee: Infineon Technologies AG
    Inventors: Mark Pavier, Wolfram Hable, Angela Kessler, Michael Sielaff, Anton Pugatschow, Charles Rimbert-Riviere, Marco Sobkowiak
  • Publication number: 20190006260
    Abstract: A method of manufacturing a package, wherein the method comprises a forming a chip carrier by covering a thermally conductive and electrically insulating core on both opposing main surfaces thereof at least partially by a respective electrically conductive layer by brazing the respective electrically conductive layer on a respective one of the main surfaces; a mounting at least one electronic chip on the chip carrier; an electrically coupling an electrically conductive contact structure with the at least one electronic chip; and an encapsulating part of the electrically conductive contact structure, and at least part of the chip carrier and of the at least one electronic chip by a mold-type encapsulant.
    Type: Application
    Filed: August 24, 2018
    Publication date: January 3, 2019
    Inventors: Mark PAVIER, Wolfram HABLE, Angela KESSLER, Michael SIELAFF, Anton PUGATSCHOW, Charles RIMBERT-RIVIERE, Marco SOBKOWIAK