Patents by Inventor Mark Pavier

Mark Pavier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10283432
    Abstract: A method of manufacturing a package, wherein the method comprises a forming a chip carrier by covering a thermally conductive and electrically insulating core on both opposing main surfaces thereof at least partially by a respective electrically conductive layer by brazing the respective electrically conductive layer on a respective one of the main surfaces; a mounting at least one electronic chip on the chip carrier; an electrically coupling an electrically conductive contact structure with the at least one electronic chip; and an encapsulating part of the electrically conductive contact structure, and at least part of the chip carrier and of the at least one electronic chip by a mold-type encapsulant.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: May 7, 2019
    Assignee: Infineon Technologies AG
    Inventors: Mark Pavier, Wolfram Hable, Angela Kessler, Michael Sielaff, Anton Pugatschow, Charles Rimbert-Riviere, Marco Sobkowiak
  • Publication number: 20190006260
    Abstract: A method of manufacturing a package, wherein the method comprises a forming a chip carrier by covering a thermally conductive and electrically insulating core on both opposing main surfaces thereof at least partially by a respective electrically conductive layer by brazing the respective electrically conductive layer on a respective one of the main surfaces; a mounting at least one electronic chip on the chip carrier; an electrically coupling an electrically conductive contact structure with the at least one electronic chip; and an encapsulating part of the electrically conductive contact structure, and at least part of the chip carrier and of the at least one electronic chip by a mold-type encapsulant.
    Type: Application
    Filed: August 24, 2018
    Publication date: January 3, 2019
    Inventors: Mark PAVIER, Wolfram HABLE, Angela KESSLER, Michael SIELAFF, Anton PUGATSCHOW, Charles RIMBERT-RIVIERE, Marco SOBKOWIAK
  • Publication number: 20180366380
    Abstract: A semiconductor package that includes a semiconductor die, an insulation around the die, and a conforming conductive pad coupled to an electrode of the die.
    Type: Application
    Filed: August 23, 2018
    Publication date: December 20, 2018
    Inventors: Mark Pavier, Andrew N. Sawle, Martin Standing
  • Patent number: 10103076
    Abstract: A method includes coupling a first major surface of a semiconductor die to a metallic body, depositing an insulation body over said semiconductor die, and removing a portion of said insulation body to expose a plurality of electrodes of said semiconductor die on a second major surface of said semiconductor die opposite said first surface. The method further includes forming a plurality of conductive pads over the plurality of electrodes, each conductive pad of said plurality of conductive pads providing an external connection for a respective one of said plurality of electrodes, wherein each conductive pad of said plurality of conductive pads has an area larger than an area of said respective one of said plurality of electrodes to which the respective conforming conductive pad of said plurality of conductive pads is coupled and extending over said insulation body.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: October 16, 2018
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Mark Pavier, Andrew N. Sawle, Martin Standing
  • Patent number: 10074590
    Abstract: A package which comprises a chip carrier, at least one electronic chip mounted on the chip carrier, an electrically conductive contact structure electrically coupled with the at least one electronic chip, and a mold-type encapsulant encapsulating part of the electrically conductive contact structure, and at least part of the chip carrier and of the at least one electronic chip, wherein the chip carrier comprises a thermally conductive and electrically insulating core covered on both opposing main surfaces thereof by a respective brazed electrically conductive layer.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: September 11, 2018
    Assignee: Infineon Technologies AG
    Inventors: Mark Pavier, Wolfram Hable, Angela Kessler, Michael Sielaff, Anton Pugatschow, Charles Rimbert-Riviere, Marco Sobkowiak
  • Patent number: 9673109
    Abstract: In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage having a control drain attached to the die side of the control conductive carrier. The control conductive carrier is configured to sink heat produced by the control FET into the mounting surface. The semiconductor package includes a sync conductive carrier having another die side and another opposite I/O side connecting the semiconductor package to the mounting surface, and a sync FET of the power converter switching stage having a sync source attached to the die side of the sync conductive carrier.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: June 6, 2017
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Eung San Cho, Andrew N. Sawle, Mark Pavier, Daniel Cutler
  • Publication number: 20170148692
    Abstract: A semiconductor package that includes a semiconductor die, an insulation around the die, and a conforming conductive pad coupled to an electrode of the die.
    Type: Application
    Filed: February 6, 2017
    Publication date: May 25, 2017
    Inventors: Mark Pavier, Andrew N. Sawle, Martin Standing
  • Patent number: 9633951
    Abstract: A semiconductor package that includes a semiconductor die, an insulation around the die, and a conforming conductive pad coupled to an electrode of the die.
    Type: Grant
    Filed: November 10, 2006
    Date of Patent: April 25, 2017
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Mark Pavier, Andrew N. Sawle, Martin Standing
  • Patent number: 9576887
    Abstract: In one implementation, a semiconductor package including conductive carrier coupled power switches includes a first vertical FET in a first active die having a first source and a first gate on a source side of the first active die and a first drain on a drain side of the first active die. The semiconductor package also includes a second vertical FET in a second active die having a second source and a second gate on a source side of the second active die and a second drain on a drain side of the second active die. The semiconductor package includes a conductive carrier attached to the source side of the first active die and to the drain side of the second active die, the conductive carrier coupling the first source to the second drain.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: February 21, 2017
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Eung San Cho, Andrew N. Sawle, Mark Pavier, Daniel Cutler
  • Patent number: 9502395
    Abstract: In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage attached to the die side of the control conductive carrier, and a driver integrated circuit (IC) for driving the control FET. The driver IC is situated above the control FET and is electrically coupled to the control FET by at least one conductive buildup layer formed over the control conductive carrier.
    Type: Grant
    Filed: October 6, 2015
    Date of Patent: November 22, 2016
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Eung San Cho, Andrew N. Sawle, Mark Pavier, Daniel Cutler
  • Patent number: 9397212
    Abstract: In one implementation, a semiconductor package includes a top-drain vertical FET in a first active die, a source of the top-drain vertical FET situated on a source side of the first active die and a drain and a gate of the top-drain vertical FET situated on a drain side of the first active die. The semiconductor package also includes a bottom-drain vertical FET in a second active die, a source and a gate of the bottom-drain vertical FET situated on a source side of the second active die and a drain of the bottom-drain vertical FET situated on a drain side of the second active die. The semiconductor package includes a conductive carrier attached to the source side of the first active die and to the drain side of the second active die, the conductive carrier coupling the source of the top-drain vertical FET to the drain of the bottom-drain vertical FET.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: July 19, 2016
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Eung San Cho, Andrew N. Sawle, Mark Pavier, Daniel Cutler
  • Patent number: 9362221
    Abstract: According to an exemplary implementation, a power component includes a component substrate and a power semiconductor device electrically and mechanically coupled to the component substrate. The power component also includes at least one first peripheral contact and at least one second peripheral contact situated on the component substrate. A power semiconductor device is situated between the at least one first peripheral contact and the at least one second peripheral contact. The at least one first peripheral contact, the at least one second peripheral contact, and a surface electrode of the power semiconductor device are configured for surface mounting. The at least one first peripheral contact can be electrically coupled to the power semiconductor device.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: June 7, 2016
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Mark Pavier, Daniel Cutler, Scott Palmer, Clive O'Dell, Rupert Burbidge
  • Publication number: 20160155674
    Abstract: In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage having a control drain attached to the die side of the control conductive carrier. The control conductive carrier is configured to sink heat produced by the control FET into the mounting surface. The semiconductor package includes a sync conductive carrier having another die side and another opposite I/O side connecting the semiconductor package to the mounting surface, and a sync FET of the power converter switching stage having a sync source attached to the die side of the sync conductive carrier.
    Type: Application
    Filed: February 9, 2016
    Publication date: June 2, 2016
    Inventors: EUNG SAN CHO, ANDREW N. SAWLE, MARK PAVIER, DANIEL CUTLER
  • Patent number: 9299690
    Abstract: In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage attached to the die side of the control conductive carrier, and a driver integrated circuit (IC) for driving the control FET. The driver IC is situated above the control FET and is electrically coupled to the control FET by at least one conductive buildup layer formed over the control conductive carrier.
    Type: Grant
    Filed: October 6, 2015
    Date of Patent: March 29, 2016
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Eung San Cho, Andrew N. Sawle, Mark Pavier, Daniel Cutler
  • Patent number: 9269655
    Abstract: In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage having a control drain attached to the die side of the control conductive carrier. The control conductive carrier is configured to sink heat produced by the control FET into the mounting surface. The semiconductor package includes a sync conductive carrier having another die side and another opposite I/O side connecting the semiconductor package to the mounting surface, and a sync FET of the power converter switching stage having a sync source attached to the die side of the sync conductive carrier.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: February 23, 2016
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Eung San Cho, Andrew N. Sawle, Mark Pavier, Daniel Cutler
  • Publication number: 20160035699
    Abstract: In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage attached to the die side of the control conductive carrier, and a driver integrated circuit (IC) for driving the control FET. The driver IC is situated above the control FET and is electrically coupled to the control FET by at least one conductive buildup layer formed over the control conductive carrier.
    Type: Application
    Filed: October 6, 2015
    Publication date: February 4, 2016
    Inventors: Eung San Cho, Andrew N. Sawle, Mark Pavier, Daniel Cutler
  • Publication number: 20160027767
    Abstract: In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage attached to the die side of the control conductive carrier, and a driver integrated circuit (IC) for driving the control FET. The driver IC is situated above the control FET and is electrically coupled to the control FET by at least one conductive buildup layer formed over the control conductive carrier.
    Type: Application
    Filed: October 6, 2015
    Publication date: January 28, 2016
    Inventors: Eung San Cho, Andrew N. Sawle, Mark Pavier, Daniel Cutler
  • Publication number: 20150348888
    Abstract: In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage having a control drain attached to the die side of the control conductive carrier. The control conductive carrier is configured to sink heat produced by the control FET into the mounting surface. The semiconductor package includes a sync conductive carrier having another die side and another opposite I/O side connecting the semiconductor package to the mounting surface, and a sync FET of the power converter switching stage having a sync source attached to the die side of the sync conductive carrier.
    Type: Application
    Filed: August 13, 2015
    Publication date: December 3, 2015
    Inventors: Eung San Cho, Andrew N. Sawle, Mark Pavier, Daniel Cutler
  • Publication number: 20150348887
    Abstract: In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage having a control drain attached to the die side of the control conductive carrier. The control conductive carrier is configured to sink heat produced by the control FET into the mounting surface. The semiconductor package includes a sync conductive carrier having another die side and another opposite I/O side connecting the semiconductor package to the mounting surface, and a sync FET of the power converter switching stage having a sync source attached to the die side of the sync conductive carrier.
    Type: Application
    Filed: August 13, 2015
    Publication date: December 3, 2015
    Inventors: Eung San Cho, Andrew N. Sawle, Mark Pavier, Daniel Cutler
  • Patent number: 9159703
    Abstract: In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage attached to the die side of the control conductive carrier, and a driver integrated circuit (IC) for driving the control FET. The driver IC is situated above the control FET and is electrically coupled to the control FET by at least one conductive buildup layer formed over the control conductive carrier.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: October 13, 2015
    Assignee: International Rectifier Corporation
    Inventors: Eung San Cho, Andrew N. Sawle, Mark Pavier, Daniel Cutler