Patents by Inventor Mark Pavier

Mark Pavier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7274100
    Abstract: An integrated circuit which includes a circuit board having passive elements embedded in its body.
    Type: Grant
    Filed: June 23, 2004
    Date of Patent: September 25, 2007
    Assignee: International Rectifier Corporation
    Inventors: Mark Pavier, Tim Sammon
  • Publication number: 20070194441
    Abstract: A semiconductor package has a thinned semiconductor die fixed in a shallow opening in a conductive body. The die electrodes at the bottom of the die are plated with a redistributed contact which overlaps the die bottom contact and an insulation body which fills the annular gap between the die and opening. A process is described for the manufacture of the package in which plural spaced openings in a lead frame body and are simultaneously processed and singulated at the end of the process.
    Type: Application
    Filed: April 20, 2007
    Publication date: August 23, 2007
    Inventor: Mark Pavier
  • Patent number: 7250672
    Abstract: A semiconductor package that includes two semiconductor die each disposed on a respective die pad and a large tracking distance interposed between at least two leads of the package for better creepage characteristics.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: July 31, 2007
    Assignee: International Rectifier Corporation
    Inventors: Mark Pavier, Ajit Dubhashi, Jorge Cerezo, Leigh Cormie, Vijay Bolloju
  • Patent number: 7235877
    Abstract: A semiconductor package has a thinned semiconductor die fixed in a shallow opening in a conductive body. The die electrodes at the bottom of the die are plated with a redistributed contact which overlaps the die bottom contact and an insulation body which fills the annular gap between the die and opening. A process is described for the manufacture of the package in which plural spaced openings in a lead frame body and are simultaneously processed and singulated at the end of the process.
    Type: Grant
    Filed: September 21, 2005
    Date of Patent: June 26, 2007
    Assignee: International Rectifier Corporation
    Inventor: Mark Pavier
  • Patent number: 7227198
    Abstract: A semiconductor package that includes two power semiconductor dies, such as power MOSFET dies, including vertical conduction MOSFETs, arranged in a half-bridge configuration is disclosed. The package may be mounted on a split conductive pad including two isolated die pads, each die pad being electrically connected to the second power electrode of the die that is on it. The split pad may include several conductive leads, including at least one output lead electrically connected to a first electrode of the first semiconductor die on the same side of the die as the control electrode and to the second electrode of the second die located on the opposite side of the second die from the control electrode.
    Type: Grant
    Filed: August 11, 2005
    Date of Patent: June 5, 2007
    Assignee: International Rectifier Corporation
    Inventors: Mark Pavier, Ajit Dubhashi, Norman G. Connah, Jorge Cerezo
  • Publication number: 20070108585
    Abstract: A semiconductor package that includes a semiconductor die, an insulation around the die, and a conforming conductive pad coupled to an electrode of the die.
    Type: Application
    Filed: November 10, 2006
    Publication date: May 17, 2007
    Inventors: Mark Pavier, Andrew Sawle, Martin Standing
  • Publication number: 20070096274
    Abstract: An insulated metal substrate composite has a patterned conductive layer on one surface and receives one or more electrodes of MOSFETs or other die on the patterned segments which lead to the edge of the IMS. The outer periphery of the IMS is cupped or bent to form a shallow can with two or more die fixed to and thermally coupled to the flat web of the can while electrodes on the die surfaces thermally coupled to the web of the can lead to terminals on the rim of the can which are coplanar with the bottom surfaces of the die. The electrodes can be externally or internally connected to form a half bridge circuit.
    Type: Application
    Filed: November 2, 2006
    Publication date: May 3, 2007
    Inventors: Mark Pavier, David Bushnell
  • Publication number: 20070096299
    Abstract: A multi chip housing has a lead frame to which plural die are soldered. A heat spreader conductive cap encloses a volume containing the plural die or chips and is fixed to the periphery of the lead frame. The tops of the die are closely spaced from the interior of the cap and the volume is filled with a thermally conductive, electrically insulating plastic encapsulant.
    Type: Application
    Filed: November 1, 2006
    Publication date: May 3, 2007
    Inventor: Mark Pavier
  • Publication number: 20070099343
    Abstract: A method for fabricating a semiconductor package which includes coupling an electrode of a semiconductor device to a portion of a lead frame, overmolding at least a portion of the die, and then removing a portion of the die to obtain a desired thickness.
    Type: Application
    Filed: November 3, 2006
    Publication date: May 3, 2007
    Inventor: Mark Pavier
  • Publication number: 20070096270
    Abstract: A multi chip housing has a lead frame to which plural die are soldered. A heat spreader conductive cap encloses a volume containing the plural die or chips and is fixed to the periphery of the lead frame. The die may be silicon or GaN based MOSFETs or integrated circuits or a mixture thereof. The tops of the die are closely spaced from the interior of the cap and the volume is filled with a thermally conductive, electrically insulating plastic encapsulant. One die can be connected to the clip as well as the lead frame and the other may be an IC die insulated from the clip.
    Type: Application
    Filed: November 2, 2006
    Publication date: May 3, 2007
    Inventor: Mark Pavier
  • Publication number: 20060261473
    Abstract: A semiconductor device package includes a substrate with one or more pads and at least one semiconductor device that has one or more of its electrodes electrically connected to the substrate pads. The package also includes one or more terminals in electrical connection with the substrate pads and that provide for external connection to the device.
    Type: Application
    Filed: April 24, 2006
    Publication date: November 23, 2006
    Inventors: Norman Connah, Mark Pavier, Phillip Adamson, Hazel Schofield
  • Publication number: 20060249836
    Abstract: A semiconductor package including a conductive clip preferably in the shape of a can, a semiconductor die, and a conductive stack interposed between the die and the interior of the can which includes a conductive platform and a conductive adhesive body.
    Type: Application
    Filed: April 21, 2006
    Publication date: November 9, 2006
    Inventors: Andy Farlow, Mark Pavier, Andrew Sawle, George Pearson, Martin Standing
  • Publication number: 20060237825
    Abstract: A semiconductor device package includes a die pad, a substrate disposed on the die pad, and a III-nitride based semiconductor device disposed on the substrate. The device package may also include a second semiconductor device disposed on the die pad or the substrate, which device may be electrically connected to the III-nitride based device to form a circuit.
    Type: Application
    Filed: April 24, 2006
    Publication date: October 26, 2006
    Inventors: Mark Pavier, Norman Connah
  • Publication number: 20060205112
    Abstract: A semiconductor package fabrication method in which drop on demand deposition of a drop on demand depositable material is used to prepare one component or a plurality of components of a semiconductor package or multi-chip module.
    Type: Application
    Filed: March 3, 2006
    Publication date: September 14, 2006
    Inventors: Martin Standing, Mark Pavier, Robert Clarke, Andrew Sawle, Kenneth McCartney
  • Patent number: 7095099
    Abstract: A low profile semiconductor device package includes a lead frame with terminal leads and two die pads for receiving at least two semiconductor die that are interconnected to form a circuit. A further low profile semiconductor device package includes a lead frame with two die pads for receiving at least two semiconductor die that are interconnected to form a circuit and also has a reduced height through removal of a mounting tab. An example of such device packages is a package that includes first and second MOSFET die, each connected to a respective die pad. The source of one MOSFET is connected to the drain of the other MOSFET, thereby forming a low profile device package that provides a half-bridge circuit. Other example device packages include different arrangements of two interconnected MOSFET die, two interconnected IGBTs, or a combination of a MOSFET die and a diode.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: August 22, 2006
    Assignee: International Rectifier Corporation
    Inventors: Stephen Oliver, Marco Soldano, Mark Pavier, Glyn Connah, Ajit Dubhashi
  • Publication number: 20060152323
    Abstract: An embedded inductor which includes a spiral conductive inductor embedded in a magnetically permeable body composed of particles of pre-sintered magnetically permeable (e.g. ferromagnetic) material and an epoxy binder.
    Type: Application
    Filed: March 14, 2006
    Publication date: July 13, 2006
    Inventor: Mark Pavier
  • Patent number: 7034344
    Abstract: An integrated semiconductor device which includes a plurality of power semiconductor devices formed in a common semiconductor die.
    Type: Grant
    Filed: July 8, 2004
    Date of Patent: April 25, 2006
    Assignee: International Rectifier Corporation
    Inventors: Mark Pavier, Tim Sammon, Chris Davis
  • Publication number: 20060060891
    Abstract: A semiconductor package has a thinned semiconductor die fixed in a shallow opening in a conductive body. The die electrodes at the bottom of the die are plated with a redistributed contact which overlaps the die bottom contact and an insulation body which fills the annular gap between the die and opening. A process is described for the manufacture of the package in which plural spaced openings in a lead frame body and are simultaneously processed and singulated at the end of the process.
    Type: Application
    Filed: September 21, 2005
    Publication date: March 23, 2006
    Inventor: Mark Pavier
  • Publication number: 20060049514
    Abstract: A semiconductor device that includes an electrode of one material and a conductive material of lower resistivity formed over the electrode and a process for fabricating the semiconductor device.
    Type: Application
    Filed: June 15, 2005
    Publication date: March 9, 2006
    Inventors: Sven Fuchs, Mark Pavier
  • Publication number: 20060033122
    Abstract: A semiconductor package which includes two power semiconductor die arranged in a half-bridge configuration.
    Type: Application
    Filed: August 11, 2005
    Publication date: February 16, 2006
    Inventors: Mark Pavier, Ajit Dubhashi, Norman Connah, Jorge Cerezo