Abstract: The present invention provides, in one embodiment, a process for fabricating a metal gate stack (200) for a semiconductor device (205). The process includes depositing a metal layer (210) over a gate dielectric layer (215) located over a semiconductor substrate (220). The process further includes forming a polysilicon layer (225) over the metal layer (210) and creating a protective layer (230) over the polysilicon layer (225). The process also includes placing an inorganic anti-reflective coating (235) over the protective layer (230). Other embodiments include a metal gate stack precursor structure (100) and a method of manufacturing an integrated circuit (300).

Abstract: Methods are disclosed for treating deposited gate dielectric materials, in which the deposited dielectric is subjected to one or more non-oxidizing anneals to densify the material, one or more oxidizing anneals to mitigate material defects, and to a nitridation process to introduce nitrogen into the gate dielectric. The annealing may be performed before and/or after the nitridation to mitigate deposition and/or nitridation defects and to densify the material while mitigating formation of unwanted low dielectric constant oxides at the interface between the gate dielectric and the semiconductor substrate.

Abstract: The present invention provides a system for producing a triple-gate transistor segment (300), utilizing a standard semiconductor substrate (302). The substrate has a plurality of isolation regions (304) formed along its upper surface in a distally separate relationship, defining a channel region (306). A form structure (308) is disposed atop the isolation regions, and defines a channel body area (310) over the channel region. A channel body structure (316) is disposed within the channel body area, and is engineered to provide a blunted corner or edge (318) along a perimeter of its upper exposed surface. The form structure is then removed, and subsequent processing is performed.

Abstract: A system and method for manufacturing semiconductor devices with dielectric layers having a dielectric constant greater than silicon dioxide includes depositing a dielectric layer on a substrate and subjecting the dielectric layer to a plasma to reduce top surface roughness in the dielectric layer.

Abstract: A dielectric layer (50) is formed over a semiconductor (10) that contains a first region (20) and a second region (30). A polysilicon layer is formed over the dielectric layer (50) and over the first region (20) and the second region (30). The polysilicon layer can comprise 0 to 50 atomic percent of germanium. A metal layer is formed over the polysilicon layer and one of the regions and reacted with the underlying polysilicon layer to form a metal silicide or a metal germano silicide. The polysilicon and metal silicide or germano silicide regions are etched to form transistor gate regions (60) and (90) respectively. If desired a cladding layer (100) can be formed above the metal gate structures.

Abstract: CMOS gate structure with metal gates having differing work functions by texture differences between NMOS and PMOS gates.

Abstract: The present invention provides, in one embodiment, a gate structure (100). The gate structure comprises a gate dielectric (105) and a gate (110). The gate dielectric includes a refractory metal and is located over a semiconductor substrate (115). The semiconductor substrate has a conduction band and a valence band. The gate is located over the gate dielectric and includes the refractory metal. The gate has a work function aligned toward the conduction band or the valence band. Other embodiments include an alternative gate structure (200), a method of forming a gate structure (300) for a semiconductor device (301) and a dual gate integrated circuit (400).

Abstract: The present invention pertains to forming a transistor in the absence of hydrogen, or in the presence of a significantly reduced amount of hydrogen. In this manner, a high-k material can be utilized to form a gate dielectric layer in the transistor and facilitate device scaling while mitigating defects that can be introduced into the high-k material by the presence of hydrogen and/or hydrogen containing compounds.

Abstract: A MOSFET structure with high-k gate dielectric layer and silicon or metal gates, amorphizing treatment of the high-k gate dielectric layer as with a plasma or ion implantation.

Abstract: The present invention provides a system for producing a triple-gate transistor segment (300), utilizing a standard semiconductor substrate (302). The substrate has a plurality of isolation regions (304) formed along its upper surface in a distally separate relationship, defining a channel region (306). A form structure (308) is disposed atop the isolation regions, and defines a channel body area (310) over the channel region. A channel body structure (316) is disposed within the channel body area, and is engineered to provide a blunted corner or edge (318) along a perimeter of its upper exposed surface. The form structure is then removed, and subsequent processing is performed.

Abstract: A method and system for performing metal-organic chemical vapor deposition (MOCVD). The method introduces a metal-organic compound into the CVD chamber in the presence of a first reactant selected to have a reducing chemistry and then, subsequently, a second reactant selected to have an oxidizing chemistry. The reducing chemistry results in deposition of metal species having a reduced surface mobility creating more uniform coverage and better adhesion. The oxidizing species results in deposition of metal species having a greater surface mobility leading to greater surface agglomeration and faster growth. By alternating the two reacts, faster growth is achieved and uniformity of the metal structure is enhanced.

Abstract: An embodiment of the invention is a gate electrode 70 having a nitrided high work function metal alloy 170 and a low work function nitrided metal alloy 190. Another embodiment of the invention is a method of manufacturing a gate electrode 70 that includes forming and then patterning and etching a layer of high work function nitrided metal alloy 170, forming a layer of low work function nitrided metal alloy 190, and then patterning and etching layers 170 and 190.

Abstract: A method of forming a first and second transistor. The method provides a semiconductor surface (20). The method also forms a gate dielectric (30) adjacent the semiconductor surface. Further, the method forms a first transistor gate electrode (902) comprising a metal portion (402) in a fixed relationship with respect to the gate dielectric. Still further, the method forms a second transistor gate electrode (901) comprising a silicide (701) of the metal portion in a fixed relationship with respect to the gate dielectric.

Abstract: The present invention pertains to methods for forming high quality thin interface oxide layers suitable for use with high-k gate dielectrics in the manufacture of semiconductor devices. An ambient that contains oxygen and a reducing agent is utilized to grow the layers. The oxygen facilitates growth of the layers, while the reducing agent simultaneously counteracts that growth. The rate of growth of the layers can thus be controlled by regulating the partial pressure of the reducing agent, which is the fraction of the reducing agent in the gas phase times the total pressure. Controlling and slowing the growth rate of the layers facilitates production of the layers to thicknesses of about 10 Angstroms or less at temperatures of about 850 degrees Celsius or more. Growing the layers at high temperatures facilitates better bonding and production of higher quality layers, which in turn yields better performing and more reliable resulting products.

Abstract: A method of forming a first and second transistors with differing work function gates by differing metals deposited to react with a silicon or silicon-germanium gate layer.

Abstract: The present invention pertains to methods for forming high quality thin interface oxide layers suitable for use with high-k gate dielectrics in the manufacture of semiconductor devices. An ambient that contains oxygen and a reducing agent is utilized to grow the layers. The oxygen facilitates growth of the layers, while the reducing agent simultaneously counteracts that growth. The rate of growth of the layers can thus be controlled by regulating the partial pressure of the reducing agent, which is the fraction of the reducing agent in the gas phase times the total pressure. Controlling and slowing the growth rate of the layers facilitates production of the layers to thicknesses of about 10 Angstroms or less at temperatures of about 850 degrees Celsius or more. Growing the layers at high temperatures facilitates better bonding and production of higher quality layers, which in turn yields better performing and more reliable resulting products.

Abstract: A method for improving high-&kgr; gate dielectric film (104) properties. The high-&kgr; film (104) is subjected to a two step anneal sequence. The first anneal is a high temperature anneal in a non-oxidizing ambient (106) such as N2 to densify the high-&kgr; film (104). The second anneal is a lower temperature anneal in an oxidizing ambient (108) to perform a mild oxidation that heals the high-&kgr; film and reduces interface defects.

Abstract: An embodiment of the invention is a gate electrode 70 having a nitrided high work function metal alloy 170 and a low work function nitrided metal alloy 190. Another embodiment of the invention is a method of manufacturing a gate electrode 70 that includes forming and then patterning and etching a layer of high work function nitrided metal alloy 170, forming a layer of low work function nitrided metal alloy 190, and then patterning and etching layers 170 and 190.

Abstract: High-k transistor gate structures and fabrication methods therefor are provided, wherein a gate dielectric interface region near a semiconductor substrate is provided with very little or no nitrogen, while the bulk high-k dielectric is provided with a uniform nitrogen concentration.

Abstract: A MOSFSET structure with high-k gate dielecttrics for silicon or metal gates with gate dielectric liquid-based oxidation surface treatments prior to gate material desposition and gate formation.