Abstract: A method of forming a first and second transistors with differing work function gates by differing metals with a second metal selectively implanted or diffused into a first metal.

Abstract: A method and system for performing metal-organic chemical vapor deposition (MOCVD). The method introduces a metal-organic compound into the CVD chamber in the presence of a first reactant selected to have a reducing chemistry and then, subsequently, a second reactant selected to have an oxidizing chemistry. The reducing chemistry results in deposition of metal species having a reduced surface mobility creating more uniform coverage and better adhesion. The oxidizing species results in deposition of metal species having a greater surface mobility leading to greater surface agglomeration and faster growth. By alternating the two reacts, faster growth is achieved and uniformity of the metal structure is enhanced.

Abstract: A method for annealing a high dielectric constant (high-k) gate dielectric layer includes placing a wafer including one or more partially formed transistors in an ambient. The ambient may include hydrogen and an oxidizing gas or the ambient may include nitrous oxide. Each transistor includes a high-k gate dielectric layer coupled to a substrate. The method further includes heating the high-k gate dielectric layer to a temperature greater than 650° C. while the gate dielectric layer is in the ambient. The ambient prevents or reduces the formation of lower dielectric constant (lower-k) material between the high-k gate dielectric layer and the substrate. Another method for annealing a high-k gate dielectric layer includes the use of an ambient including chemically active oxygen gas. When such an ambient is used, the high-k gate dielectric layer is heated to a temperature not greater than 600° C. while the gate dielectric layer is in the ambient.

Abstract: A method is provided for forming dual work function gate electrodes. A dielectric layer is provided outwardly of a substrate. A metal layer is formed outwardly of the dielectric layer. A silicon-germanium layer is formed outwardly of the metal layer. A first portion of the silicon-germanium layer is removed to expose a first portion of the metal layer, with a second portion of the silicon-germanium layer remaining over a second portion of the metal layer. A silicon-germanium metal compound layer is formed from the second portion of the silicon-germanium layer and the second portion of the metal layer. A first gate electrode comprising the first portion of the metal layer is formed. A second gate electrode comprising the silicon-germanium metal compound layer is formed.

Abstract: A MOSFET structure with high-k gate dielectrics for silicon or metal gates with gate dielectric liquid-based oxidation surface treatments prior to gate material deposition and gate formation.

Abstract: In part, disclosed are semiconductor processing methods, methods of depositing a tungsten comprising layer over a substrate, methods of depositing a tungsten nitride comprising layer over a substrate, methods of depositing a tungsten silicide comprising layer over a substrate, methods of forming a transistor gate line over a substrate, methods of forming a patterned substantially crystalline Ta2O5 comprising material, and methods of forming a capacitor dielectric region comprising substantially crystalline Ta2O5 comprising material. In one implementation, a semiconductor processing method includes forming a substantially amorphous Ta2O5 comprising layer over a semiconductive substrate. The layer is exposed to WF6 under conditions effective to etch substantially amorphous Ta2O5 from the substrate.

Abstract: A method for annealing a high dielectric constant (high-k) gate dielectric layer includes placing a wafer including one or more partially formed transistors in an ambient. The ambient may include hydrogen and an oxidizing gas or the ambient may include nitrous oxide. Each transistor includes a high-k gate dielectric layer coupled to a substrate. The method further includes heating the high-k gate dielectric layer to a temperature greater than 650° C. while the gate dielectric layer is in the ambient. The ambient prevents or reduces the formation of lower dielectric constant (lower-k) material between the high-k gate dielectric layer and the substrate. Another method for annealing a high-k gate dielectric layer includes the use of an ambient including chemically active oxygen gas. When such an ambient is used, the high-k gate dielectric layer is heated to a temperature not greater than 600° C. while the gate dielectric layer is in the ambient.

Abstract: A method of forming a first and second transistor. The method provides a semiconductor surface (20). The method also forms a gate dielectric (30) adjacent the semiconductor surface. Further, the method forms a first transistor gate electrode (902) comprising a metal portion (402) in a fixed relationship with respect to the gate dielectric. Still further, the method forms a second transistor gate electrode (901) comprising a silicide (701) of the metal portion in a fixed relationship with respect to the gate dielectric.

Abstract: The present invention provides methods for the preparation of ruthenium metal films from liquid ruthenium complexes of the formula (diene)Ru(CO)3, wherein “diene” refers to linear, branched, or cyclic dienes, bicyclic dienes, tricyclic dienes, fluorinated derivatives thereof, combinations thereof, or derivatives thereof additionally containing heteroatoms such as halide, Si, S, Se, P, As, N, or O, in the presence of an oxidizing gas.

Abstract: The present invention provides methods for the preparation of ruthenium metal films from liquid ruthenium complexes of the formula (diene)Ru(CO)3, wherein “diene” refers to linear, branched, or cyclic dienes, bicyclic dienes, tricyclic dienes, fluorinated derivatives thereof, combinations thereof, or derivatives thereof additionally containing heteroatoms such as halide, Si, S, Se, P, As, N, or O, in the presence of an oxidizing gas.

Abstract: A plug is formed of polysilicon, or other oxidizable conductor. Chemical-mechanical polishing is performed, with a polish stop layer defining the top of the dielectric layer. The upper portion of the polysilicon is oxidized to a controlled depth, then the oxidized portion is removed by an etch, followed by removal of the polish stop layer. The plug thus formed protrudes a controllable distance above the surrounding dielectric, providing good contact to subsequent conductive layers.

Abstract: An adherent hardmask structure and method of etching a bottom electrode in memory device capacitor structures that dispenses with the need for any adhesion promoter during the etching of the bottom electrode. By using silicon nitride as a hardmask 220, the processing is simplified and a more robust capacitor structure can be produced. Silicon nitride 220 has been shown to yield significantly enhanced adhesion to platinum 210, as compared to silicon oxide formed by any method. Since silicon nitride 220 is oxidation resistant, it advantageously resists any oxygen plasma that might be used in the etch chemistry. This etching process can be used during processing of high-k capacitor structures in DRAMs in the ≧256 Mbit generations.

Abstract: An encapsulated gate structure includes a polysilicon layer, a barrier layer overlying the polysilicon layer and having opposing sidewalls, a metal layer overlying the barrier layer and having opposing sidewalls, a top dielectric layer overlying the metal layer and having opposing sidewalls, and a vertically oriented dielectric layer extending over and covering each of the opposing sidewalls of the barrier layer and the metal layer to encapsulate the barrier layer and metal layer on the polysilicon layer. The encapsulated gate and barrier layer are thus unaffected by oxidation and other similar detrimental effects of subsequent processing steps.

Abstract: A high-selectivity via etching process. The process includes the steps of: forming an etchstop layer 840 of a material selected from the group consisting of Ti--Al, Ti--Al--N, Ta--Al, Al--N, Ti--Al/Ti--N, Ti--Al--N/Ti--N, Ta--Al/Ti--N, and Ti--Al/Ti--Al--N; forming a dielectric layer over the etchstop layer; and etching the dielectric layer with a fluorine-bearing etchant.

Abstract: A high-k dielectric capacitor structure and fabrication method that incorporates an adhesion promoting etch stop layer 200 to promote adhesion of the bottom electrode 220 to the interlevel dielectric layer 210 and to provide a well controlled, repeatable and uniform recess prior to the dielectric 230 deposition. By using a sacrificial layer 200, for example silicon nitride (Si3N4), this layer can act as an etch stop during the recess etch to eliminate parasitic capacitance between adjacent capacitor cells A and B and can promote adhesion of the bottom electrode material 220 to the substrate 210.

Abstract: A method for making oriented thin films of a ternary intermetallic compound and such films having a tetragonal structure and generally uniaxial magnetic, optical, electronic, and mechanical properties, as well as a generally lower Curie temperature than oriented binary intermetallic films. The steps of the method involve selecting a substrate material for biasing the orientation of the ternary intermetallic compound and exhibiting no chemical reactiveness to the ternary intermetallic compound. Preferably, such substrate is a single crystal, such as MgO or Al.sub.2 O.sub.3, or an amorphous material such as pure SiO.sub.2, amorphous carbon, or glass. In a second step the substrate is heated to a temperature above 450.degree. C. and then, a first metal, a second metal, and a third metal are simultaneously deposited on the substrate material.

Abstract: A method for producing oriented, intermetallic, thin film structures having uniaxial magnetic, electronic, optical, and mechanical properties. Artificial superlattices (10) are assembled by sputter deposition of alternating layers of the component metals of the target intermetallic compound on an aligned substrate (16). Either single crystal substrates or crystallographically textured substrates may be used to induce alignment of the deposited layers (10, 12) in the method of the present invention. Annealing of the resulting superlattice (10) generates aligned, thin film intermetallic compounds (38) of the component metals at the interfaces (44) of the superlattice (10), the thin film intermetallic compounds having pronounced, uniaxial properties.