Patents by Inventor Mark S. Johnson
Mark S. Johnson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6820525Abstract: A fiducial includes complementary patterns that are situated symmetrically about a common axis. The complementary patterns permit location of the common axis as an axis that is equidistant from the complementary patterns. The complementary patterns are displaced from the common axes by different distances so that the common axis is located using the complementary patterns nearest the common axis to accurately locate the common axis. The complementary patterns include etch-compensation features that permit the common axis to be accurately located even if an etch process defines the fiducial and the etch process exhibits a process error or variation such as underetching or overetching. The fiducial may be produced by transferring a fiducial pattern from a mask such as a photomask. The fiducial pattern may also be defined on the mask using a computer-aided design program.Type: GrantFiled: October 11, 2002Date of Patent: November 23, 2004Assignee: Micron Technology, Inc.Inventor: Mark S. Johnson
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Publication number: 20040130008Abstract: The present invention provides microelectronic component assemblies and lead frame structures that may be useful in such assemblies. For example, one such lead frame structure may include a set of leads extending in a first direction and a dam bar. Each of the leads may have an outer length and an outer edge. The dam bar may include a plurality of dam bar elements, with each dam bar element being joined to the outer lengths of two adjacent leads. In this example, each dam bar element has an outer edge that extends farther outwardly than the outer edges of the two adjacent leads. The outer edges of the leads and the outer edges of the dam bar elements together define an irregular outer edge of the dam bar. Other lead frame structures and various microelectronic component assemblies are also shown and described.Type: ApplicationFiled: January 6, 2003Publication date: July 8, 2004Inventor: Mark S. Johnson
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Patent number: 6632575Abstract: A fiducial includes complementary patterns that are situated symmetrically about a common axis. The complementary patterns permit location of the common axis as an axis that is equidistant from the complementary patterns. The complementary patterns are displaced from the common axes by different distances so that the common axis is located using the complementary patterns nearest the common axis to accurately locate the common axis. The complementary patterns include etch-compensation features that permit the common axis to be accurately located even if an etch process defines the fiducial and the etch process exhibits a process error or variation such as underetching or overetching. The fiducial may be produced by transferring a fiducial pattern from a mask such as a photomask. The fiducial pattern may also be defined on the mask using a computer-aided design program.Type: GrantFiled: August 31, 2000Date of Patent: October 14, 2003Assignee: Micron Technology, Inc.Inventor: Mark S. Johnson
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Patent number: 6605331Abstract: A method of encapsulating an article having first and second surfaces, includes positioning a first molding section in a sealing relationship with the first surface of the article and positioning a second molding section adjacent the second surface of the article. The first molding section is filled first thereby forcing the second surface of the article into a sealing engagement with the second molding section. The second molding section is then filled.Type: GrantFiled: September 1, 1999Date of Patent: August 12, 2003Assignee: Micron Technology, Inc.Inventors: Mark S. Johnson, Todd O. Bolken
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Patent number: 6601294Abstract: A semiconductor package with thermally enhanced properties is described. The semiconductor package includes a substrate upon which a die is affixed. The die and the substrate each have contacts which are respectively connected with each other. A heat sink is affixed to a surface of the die by way of a thermally compliant material. The compliant material reduces the stresses caused by temperature fluctuations which cause the heat sink and the die to expand and contract at different rates. A first molding material is deposited around the periphery of the die, compliant material and heat sink, thereby leaving exposed substantially an entire surface of the heat sink.Type: GrantFiled: September 29, 2000Date of Patent: August 5, 2003Assignee: Micron Technology, Inc.Inventors: Tongbi Jiang, Mark S. Johnson
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Publication number: 20030093173Abstract: A stereolithographic method and apparatus for applying packaging material to workpieces such as preformed electronic components, including semiconductor dice, with a high degree of precision, and resulting articles. A machine vision system including at least one camera is operably associated with a computer controlling a stereolithographic system for application of material so that the system may recognize the position and orientation of workpieces, such as semiconductor dice, to which the material is to be applied. The requirement for precise mechanical workpiece alignment is eliminated, and the ability of the system to recognize size, configuration and topography of different workpieces affords greater manufacturing flexibility. The method includes stereolithographic application of material for packaging electronic components, and the electronic components so packaged are also part of the invention.Type: ApplicationFiled: November 12, 2002Publication date: May 15, 2003Inventors: Warren M. Farnworth, Mark S. Johnson
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Publication number: 20030086994Abstract: A method of encapsulating an article having first and second surfaces, includes positioning a first molding section in a sealing relationship with the first surface of the article and positioning a second molding section adjacent the second surface of the article. The first molding section is filled first thereby forcing the second surface of the article into a sealing engagement with the second molding section. The second molding section is then filled.Type: ApplicationFiled: December 17, 2002Publication date: May 8, 2003Inventors: Mark S. Johnson, Todd O. Bolken
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Stereolithographic method and apparatus for packaging electronic components and resulting structures
Patent number: 6549821Abstract: A stereolithographic method and apparatus for applying packaging material to workpieces such as preformed electronic components, including semiconductor dice, with a high degree of precision, and resulting articles. A machine vision system including at least one camera is operably associated with a computer controlling a stereolithographic system for application of material so that the system may recognize the position and orientation of workpieces, such as semiconductor dice, to which the material is to be applied. The requirement for precise mechanical workpiece alignment is eliminated, and the ability of the system to recognize size, configuration and topography of different workpieces affords greater manufacturing flexibility. The method includes stereolithographic application of material for packaging electronic components, and the electronic components so packaged are also part of the invention.Type: GrantFiled: February 26, 1999Date of Patent: April 15, 2003Assignee: Micron Technology, Inc.Inventors: Warren M. Farnworth, Mark S. Johnson -
Patent number: 6541856Abstract: A high density semiconductor package with thermally enhanced properties is described. The semiconductor package includes a pair of lead frames, each being attached to a respective semiconductor die. The dies are attached to respective lead frames via an adhering material, such as a tape. Further, the dies are each electrically connected to fingers of each lead frame. In one illustrated embodiment, the dies and portions of the fingers are encapsulated in such a way as to leave one surface of each die exposed. In another illustrated embodiment, heat dissipation for the semiconductor package occurs through exposed fingers of the lead frames which adhere semiconductor dies within a cavity located therebetween.Type: GrantFiled: June 6, 2001Date of Patent: April 1, 2003Assignee: Micron Technology, Inc.Inventors: David J. Corisis, Mike Brooks, Mark S. Johnson, Larry D. Kinsman
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Patent number: 6537853Abstract: A method of encapsulating an article having first and second surfaces, includes positioning the article on a carrier such that at least a portion of the first surface contacts the carrier. A portion of the carrier carrying the article is then positioned within a mold and a seal is formed between the mold and the carrier. The mold is then filled with an encapsulating material to form a seal between the article and the carrier.Type: GrantFiled: August 31, 2000Date of Patent: March 25, 2003Assignee: Micron Technology, Inc.Inventors: Mark S. Johnson, Todd O. Bolken
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Publication number: 20030039901Abstract: A fiducial includes complementary patterns that are situated symmetrically about a common axis. The complementary patterns permit location of the common axis as an axis that is equidistant from the complementary patterns. The complementary patterns are displaced from the common axes by different distances so that the common axis is located using the complementary patterns nearest the common axis to accurately locate the common axis. The complementary patterns include etch-compensation features that permit the common axis to be accurately located even if an etch process defines the fiducial and the etch process exhibits a process error or variation such as underetching or overetching. The fiducial may be produced by transferring a fiducial pattern from a mask such as a photomask. The fiducial pattern may also be defined on the mask using a computer-aided design program.Type: ApplicationFiled: October 11, 2002Publication date: February 27, 2003Applicant: Micron Technology, Inc.Inventor: Mark S. Johnson
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Publication number: 20030030152Abstract: A high density semiconductor package with thermally enhanced properties is described. The semiconductor package includes a pair of lead frames, each being attached to a respective semiconductor die. The dies are attached to respective lead frames via an adhering material, such as a tape. Further, the dies are each electrically connected to fingers of each lead frame. In one illustrated embodiment, the dies and portions of the fingers are encapsulated in such a way as to leave one surface of each die exposed. In another illustrated embodiment, heat dissipation for the semiconductor package occurs through exposed fingers of the lead frames which adhere semiconductor dies within a cavity located therebetween.Type: ApplicationFiled: October 1, 2002Publication date: February 13, 2003Inventors: David J. Corisis, Mike Brooks, Mark S. Johnson, Larry D. Kinsman
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Publication number: 20020185729Abstract: A high density semiconductor package with thermally enhanced properties is described. The semiconductor package includes a pair of lead frames, each being attached to a respective semiconductor die. The dies are attached to respective lead frames via an adhering material, such as a tape. Further, the dies are each electrically connected to fingers of each lead frame. In one illustrated embodiment, the dies and portions of the fingers are encapsulated in such a way as to leave one surface of each die exposed. In another illustrated embodiment, heat dissipation for the semiconductor package occurs through exposed fingers of the lead frames which adhere semiconductor dies within a cavity located therebetween.Type: ApplicationFiled: June 6, 2001Publication date: December 12, 2002Inventors: David J. Corisis, Mike Brooks, Mark S. Johnson, Larry D. Kinsman
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Patent number: 6417018Abstract: The present invention relates to a method of encapsulating a plurality of chip and board pre-assemblies. Each pre-assembly has first and second surfaces. The method includes positioning a first mold half in a sealing relationship with each first surface of the pre-assemblies and positioning a second mold half adjacent each second surface of the pre-assemblies. The first mold half is filled first thereby forcing each second surface of the pre-assemblies into a sealing engagement with the second mold half. The second molding section is then filled, to result in an asymmetrically overmolded chip and board assembly.Type: GrantFiled: November 28, 2000Date of Patent: July 9, 2002Assignee: Micron Technology, Inc.Inventors: Todd O. Bolken, Mark S. Johnson
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Publication number: 20020076859Abstract: A method of encapsulating an article having first and second surfaces, includes positioning the article on a carrier such that at least a portion of the first surface contacts the carrier. A portion of the carrier carrying the article is then positioned within a mold and a seal is formed between the mold and the carrier. The mold is then filled with an encapsulating material to form a seal between the article and the carrier.Type: ApplicationFiled: November 20, 2001Publication date: June 20, 2002Inventors: Mark S. Johnson, Todd O. Bolken
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Patent number: 6294825Abstract: The present invention relates to a method and system of encapsulating a plurality of chip and board pre-assemblies. Each pre-assembly has first and second surfaces. The method includes positioning a first mold half in a sealing relationship with each first surface of the pre-assemblies and positioning a second mold half adjacent each second surface of the pre-assemblies. The first mold half is filled first thereby forceing each second surface of the pre-assemblies into a sealing engagement with the second mold half. The second molding section is then filled, to result in an asymmetrically overmolded chip and board assembly.Type: GrantFiled: August 30, 1999Date of Patent: September 25, 2001Assignee: Micron Technology, Inc.Inventors: Todd O. Bolken, Mark S. Johnson
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Patent number: 6208519Abstract: A semiconductor package with thermally enhanced properties is described. The semiconductor package includes a substrate upon which a die is affixed. The die and the substrate each have contacts which are respectively connected with each other. A heat sink is affixed to a surface of the die by way of a thermally compliant material. The compliant material reduces the stresses caused by temperature fluctuations which cause the heat sink and the die to expand and contract at different rates. A first molding material is deposited around the periphery of the die, compliant material and heat sink, thereby leaving exposed substantially an entire surface of the heat sink.Type: GrantFiled: August 31, 1999Date of Patent: March 27, 2001Assignee: Micron Technology, Inc.Inventors: Tongbi Jiang, Mark S. Johnson
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Patent number: 6176930Abstract: An apparatus and method for controlling a flow of process material to a deposition chamber. The apparatus comprises an injector valve, disposed between the process material source and the deposition chamber. The injector valve controls the flow of precursor material by repeatedly opening and closing the injector valve with a predetermined duty cycle. The apparatus further comprises an evaporator coupled to the injector valve for evaporating the precursor.Type: GrantFiled: March 4, 1999Date of Patent: January 23, 2001Assignee: Applied Materials, Inc.Inventors: Keith K. Koai, Tung-Ching Tseng, James J. Chen, Mark S. Johnson, John Schmitt, Sean Li
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Patent number: 6143581Abstract: A method of encapsulating an article having first and second surfaces, includes positioning a first molding section in a sealing relationship with the first surface of the article and positioning a second molding section adjacent the second surface of the article. The first molding section is filled first thereby forcing the second surface of the article into a sealing engagement with the second molding section. The second molding section is then filled.Type: GrantFiled: February 22, 1999Date of Patent: November 7, 2000Assignee: Micron Technology, Inc.Inventors: Mark S. Johnson, Todd O. Bolken
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Patent number: 6063441Abstract: A substrate processing chamber, particularly a chemical vapor deposition (CVD) chamber used both for thermal deposition of a conductive material and a subsequently performed plasma process. The invention reduces thermal deposition of the conductive material on peripheral portions of the pedestal supporting a wafer and in a pumping channel exhausting the chamber. A peripheral ring placed on the pedestal, preferably also used to center the wafer, is thermally isolated from the pedestal so that its temperature is kept substantially lower than that of the wafer. The processing chamber includes a chamber lid assembly having an isolator ring member that has a sloping surface for confirming the plasma within a processing zone of the processing chamber while the wafer is being processed therein. A method for forming a CVD layer on a wafer comprising elevating the pedestal until an upper pedestal surface of the pedestal extends above a lower edge of the isolator ring member.Type: GrantFiled: December 2, 1997Date of Patent: May 16, 2000Assignee: Applied Materials, Inc.Inventors: Keith Koai, Lawrence Chung-Lai Lei, Mei Chang, Mark S. Johnson