Patents by Inventor Markus Schimper
Markus Schimper has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9699014Abstract: This disclosure is directed towards techniques and methods of suppressing the effect of modulated clock jitter in a digital to analog conversion (DAC) circuit of a polar modulator in a transceiver. A phase locked loop (PLL) in a modulator circuit may introduce a deterministic jitter in DAC generated pulses which may lead to amplitude variations in the DAC generated pulses. The clock jitter may change the duty cycle of the input amplitude to the DAC which may result in a variation of the output of the DAC generated pulse. A digital pre-distortion or digital multiplier circuit may be introduced before the DAC circuit to increase or decrease the DAC amplitude to compensate for the pulse width modulation.Type: GrantFiled: March 5, 2012Date of Patent: July 4, 2017Assignee: Infineon Technologies AGInventors: Markus Schimper, Franz Kuttner
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Patent number: 9429919Abstract: A delay line operates to propagate a plurality of delay stages comprising a first delay element and a second delay element. A generator coupled to the delay line is configured to provide the start edge to the plurality of delay stages of the delay line as a function of a digital control oscillator (DCO) counter value generated by a DCO counter. A DCO calculation component is configured to facilitate a determination of propagation counts of the delay line as a function of DCO periods of a DCO.Type: GrantFiled: November 17, 2014Date of Patent: August 30, 2016Assignee: Intel Deutschland GmbHInventor: Markus Schimper
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Publication number: 20160139568Abstract: A delay line operates to propagate a plurality of delay stages comprising a first delay element and a second delay element. A generator coupled to the delay line is configured to provide the start edge to the plurality of delay stages of the delay line as a function of a digital control oscillator (DCO) counter value generated by a DCO counter. A DCO calculation component is configured to facilitate a determination of propagation counts of the delay line as a function of DCO periods of a DCO.Type: ApplicationFiled: November 17, 2014Publication date: May 19, 2016Inventor: Markus Schimper
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Patent number: 9292007Abstract: Representative implementations of devices and techniques provide bipolar time-to-digital conversion. For example, either a positive time duration or a negative time duration may be converted to a digital representation by a linear time-to-digital converter (TDC). A set of logic functions may be applied to the input of the TDC to provide start and/or stop signals for the TDC. Further, a correction component may be applied to an input or an output of the TDC to compensate for a delay offset of the TDC.Type: GrantFiled: March 2, 2015Date of Patent: March 22, 2016Assignee: Intel Deutschland GmbHInventors: Stephan Henzler, Markus Schimper, Stefan Tertinek
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Publication number: 20150365113Abstract: A modulator and associated method includes a calculation block configured to receive a plurality of digital samples of a modulated baseband signal, and determine time instances associated with predetermined phase crossings of the modulated baseband signal. The modulator further includes a converter circuit configured to generate a data dependent clock signal having rising and falling edges associated with the determined time instances, and a digital to analog converter configured to receive the data dependent clock signal and generate a square wave output signal having transition times associated with the generated data dependent clock signal.Type: ApplicationFiled: June 13, 2014Publication date: December 17, 2015Inventors: Andreas Menkhoff, Michael Bruennert, Markus Schimper
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Patent number: 9197258Abstract: A modulator and associated method includes a calculation block configured to receive a plurality of digital samples of a modulated baseband signal, and determine time instances associated with predetermined phase crossings of the modulated baseband signal. The modulator further includes a converter circuit configured to generate a data dependent clock signal having rising and falling edges associated with the determined time instances, and a digital to analog converter configured to receive the data dependent clock signal and generate a square wave output signal having transition times associated with the generated data dependent clock signal.Type: GrantFiled: June 13, 2014Date of Patent: November 24, 2015Assignee: Intel IP CorporationInventors: Andreas Menkhoff, Michael Bruennert, Markus Schimper
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Patent number: 9143155Abstract: One embodiment of the present disclosure relates to a circuit. The circuit includes a digital to analog converter (DAC) configured to convert a time-varying, multi-bit digital value to a corresponding time-varying output current. The circuit also includes a mixer module downstream of the DAC and comprising a plurality of mixers. A control block is configured to selectively steer output current from the DAC to different mixers of the mixer module. Other techniques are also described.Type: GrantFiled: December 9, 2013Date of Patent: September 22, 2015Assignee: Intel Deutschland GmbHInventors: Peter Pfann, Markus Schimper, Jose Moreira, Timo Gossmann
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Patent number: 9130588Abstract: Representative implementations of devices and techniques provide a time delay based on an input value. A digital delay may be generated based on a coarse delay and a fine delay. The coarse delay may be selected based on the input value. The fine delay may be selected from an overlapping set of fine delay intervals, based on the selected coarse delay. In some implementations, a control component may be used to select the fine delay when more than one fine delay interval is indicated.Type: GrantFiled: March 15, 2013Date of Patent: September 8, 2015Assignee: Intel Mobile Communications GmbHInventors: Stephan Henzler, Markus Schimper, Paolo Madoglio, Stefano Pellerano, Kailash Chandrashekar
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Publication number: 20150241850Abstract: Representative implementations of devices and techniques provide bipolar time-to-digital conversion. For example, either a positive time duration or a negative time duration may be converted to a digital representation by a linear time-to-digital converter (TDC). A set of logic functions may be applied to the input of the TDC to provide start and/or stop signals for the TDC. Further, a correction component may be applied to an input or an output of the TDC to compensate for a delay offset of the TDC.Type: ApplicationFiled: March 2, 2015Publication date: August 27, 2015Inventors: Stephan Henzler, Markus Schimper, Stefan Tertinek
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Patent number: 9071304Abstract: Embodiments of a digital-to-time converter (DTC) and methods for generating phase-modulated signals are generally described herein. In some embodiments, a divide by 2N+/?1 operation on an oscillator signal generates first and second divider signals, the first divider signal is sampled to provide a rising-edge correlated signal, a divider unit output signal is sampled to provide a falling edge correlated signal, and either the second divider signal or a delayed version of the second divider signal is provided as the divider unit output signal. A selection between the rising-edge and the falling-edge correlated signals generates edge signals. A fine phase-modulated output signal is generated based on an edge interpolation between a first and second edge signals.Type: GrantFiled: August 16, 2013Date of Patent: June 30, 2015Assignee: Intel IP CorporationInventors: Rotem Banin, Ofir Degani, Markus Schimper, Ashoke Ravi
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Patent number: 8994573Abstract: A digital-to-time converter (DTC) comprises a gate controller configured to generate a gate enable signal based on first and second digital values so that the gate enable signal has a first enable period and a second enable period for each pair of a first digital value and a second digital value. A gate conditionally passes a main clock signal to a gate output in response to the gate enable signal, the gate thus providing a gated signal at a gate output. A frequency divider generates a frequency divided signal as the output signal of the digital-to-time converter based on the gated signal. The DTC may be calibrated by a time-to-digital converter connected between an input for the main clock signal and an output of a delay element of the DTC.Type: GrantFiled: March 15, 2013Date of Patent: March 31, 2015Assignee: Intel Mobile Communications GmbHInventors: Stephan Henzler, Markus Schimper
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Patent number: 8970420Abstract: Representative implementations of devices and techniques provide bipolar time-to-digital conversion. For example, either a positive time duration or a negative time duration may be converted to a digital representation by a linear time-to-digital converter (TDC). A set of logic functions may be applied to the input of the TDC to provide start and/or stop signals for the TDC. Further, a correction component may be applied to an input or an output of the TDC to compensate for a delay offset of the TDC.Type: GrantFiled: March 15, 2013Date of Patent: March 3, 2015Assignee: Intel Mobile Communications GmbHInventors: Stephan Henzler, Markus Schimper, Stefan Tertinek
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Publication number: 20150049840Abstract: Embodiments of a digital-to-time converter (DTC) and methods for generating phase-modulated signals are generally described herein. In some embodiments, a divide by 2N+/?1 operation on an oscillator signal generates first and second divider signals, the first divider signal is sampled to provide a rising-edge correlated signal, a divider unit output signal is sampled to provide a falling edge correlated signal, and either the second divider signal or a delayed version of the second divider signal is provided as the divider unit output signal. A selection between the rising-edge and the falling-edge correlated signals generates edge signals. A fine phase-modulated output signal is generated based on an edge interpolation between a first and second edge signals.Type: ApplicationFiled: August 16, 2013Publication date: February 19, 2015Inventors: Rotem Banin, Ofir Degani, Markus Schimper, Ashoke Ravi
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Patent number: 8860512Abstract: A ring oscillator includes a ring of a plurality of delay elements and a start edge injector for injecting a start edge into the ring. The start edge injector varies an injection point for the start edge in the ring.Type: GrantFiled: September 28, 2012Date of Patent: October 14, 2014Assignee: Intel Mobile Communications GmbHInventor: Markus Schimper
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Publication number: 20140266837Abstract: Representative implementations of devices and techniques provide a time delay based on an input value. A digital delay may be generated based on a coarse delay and a fine delay. The coarse delay may be selected based on the input value. The fine delay may be selected from an overlapping set of fine delay intervals, based on the selected coarse delay. In some implementations, a control component may be used to select the fine delay when more than one fine delay interval is indicated.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Inventors: Stephan HENZLER, Markus SCHIMPER
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Publication number: 20140266822Abstract: A digital-to-time converter (DTC) comprises a gate controller configured to generate a gate enable signal based on first and second digital values so that the gate enable signal has a first enable period and a second enable period for each pair of a first digital value and a second digital value. A gate conditionally passes a main clock signal to a gate output in response to the gate enable signal, the gate thus providing a gated signal at a gate output. A frequency divider generates a frequency divided signal as the output signal of the digital-to-time converter based on the gated signal. The DTC may be calibrated by a time-to-digital converter connected between an input for the main clock signal and an output of a delay element of the DTC.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Inventors: Stephan Henzler, Markus Schimper
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Publication number: 20140266848Abstract: Representative implementations of devices and techniques provide bipolar time-to-digital conversion. For example, either a positive time duration or a negative time duration may be converted to a digital representation by a linear time-to-digital converter (TDC). A set of logic functions may be applied to the input of the TDC to provide start and/or stop signals for the TDC. Further, a correction component may be applied to an input or an output of the TDC to compensate for a delay offset of the TDC.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Inventors: Stephan HENZLER, Markus SCHIMPER, Stefan TERTINEK
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Patent number: 8797087Abstract: A reference quantity generator for generating a reference quantity includes a reference source configured to provide a reference source signal, a digitally controlled signal source and a digital controller. The digitally controlled signal source is configured to provide a digitally controlled quantity. The reference quantity is determined based on the digitally controlled quantity. The digital controller is configured to provide a digital control signal to control the digitally controlled signal source to adapt the digitally controlled quantity based on the reference source signal using a feedback.Type: GrantFiled: June 24, 2011Date of Patent: August 5, 2014Assignee: Intel Mobile Communications GmbHInventor: Markus Schimper
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Patent number: 8797079Abstract: A differential delay line includes a series connection of a plurality of differential delay stages. Each differential delay stage includes a first delay element and a second delay element. The first delay element has a first input, a second input and an output. The second delay element has a first input, a second input and an output. The output of the first delay element of an n-th differential delay stage of the plurality of differential delay stages is coupled to an input of the second delay element of an (n+m)-th differential delay stage of the plurality of differential delay stages, wherein m is an even natural number larger than or equal to two.Type: GrantFiled: September 28, 2012Date of Patent: August 5, 2014Assignee: Intel Mobile Communications GmbHInventor: Markus Schimper
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Patent number: 8760330Abstract: An analog-to-digital converter for converting an input signal includes a sigma-delta modulator for receiving an analog modulator input signal and for providing a digital modulator output signal and an interference cancellation loop. The interference cancellation loop includes a digital filter, a digital-to-analog converter, and a signal combiner. The digital filter is configured to amplify the sigma-delta output signal in a frequency band, attenuate the sigma-delta output signal outside the frequency band and a transition band surrounding the frequency band, and provide a filtered digital feedback signal. The digital-to-analog converter is configured to convert the filtered digital signal to a cancellation signal. The signal combiner is configured to combine the input signal with the cancellation signal resulting in the modulator input signal, in order to at least partially cancel interference signal portions within the input signal.Type: GrantFiled: January 31, 2012Date of Patent: June 24, 2014Assignee: Intel Mobile Communications GmbHInventors: Rudolf Ritter, Markus Schimper, Werner Schelmbauer, Maurits Ortsmanns