Abstract: An analogue-to-digital converter includes a summing element for combining an analogue input signal of the analogue-to-digital converter with a feedback signal in order to generate a fault signal, a quantizer which has comparators for comparing the fault signal with reference voltages in order to generate a digital output signal, a digital-to-analogue converter for converting the digital output signal into the feedback signal, a control device for generating a control signal from the digital output signal in order to control the use of elements of the digital-to-analogue converter in such a way that mismatching of the elements is compensated, a random number generating device for generating random numbers which are used in the quantizer to interchange the assignment of the reference voltages to the comparators in order to eliminate an effect of offset voltages at inputs of the comparators, and a compensation device for generating a compensated control signal from the control signal as a function of the random

Abstract: An integrated semiconductor circuit has a tunable resistor circuit whose total resistance value can be altered, the total resistance value being stipulated by a digital control word. A comparator compares a first voltage applied to the tunable resistor circuit with a second voltage applied to an external resistor element. A trimmer is coupled to the comparator and to the resistor circuit and provides the digital control word for the tunable resistor circuit. The trimmer determines that digital control word for which the resistor circuit has a total resistance value at which the first voltage is in a prescribed ratio to the second voltage.

Abstract: In one embodiment, an amplifier arrangement includes an amplifier having a first input, a second input and an output, a first resistor network, having a first parallel circuit formed by a first number N of resistors, and a second resistor network, having a first resistor or a second parallel circuit formed by a second number M of resistors. The resistors of the first and second resistor networks each have approximately the same nominal value, an approximately identical width W and an approximately identical length L of a resistive layer. The first and second resistor networks are coupled to the amplifier.

Abstract: The control apparatus (8?) is used to dynamically assign N individual references to N individual comparators of a quantizer in a sigma-delta analogue/digital converter, the control apparatus (8?) generating a digital control signal (9?). The control apparatus (8?) has a storage means (12) for providing the value of the control signal (9?) at the time k?1, and a summation means (10) for summing the output signal Y of the quantizer with the stored value of the first control signal (9?) at the time k?1.

Abstract: An analogue-to-digital converter includes a summing element for combining an analogue input signal of the analogue-to-digital converter with a feedback signal in order to generate a fault signal, a quantizer which has comparators for comparing the fault signal with reference voltages in order to generate a digital output signal, a digital-to-analogue converter for converting the digital output signal into the feedback signal, a control device for generating a control signal from the digital output signal in order to control the use of elements of the digital-to-analogue converter in such a way that mismatching of the elements is compensated, a random number generating device for generating random numbers which are used in the quantizer to interchange the assignment of the reference voltages to the comparators in order to eliminate an effect of offset voltages at inputs of the comparators, and a compensation device for generating a compensated control signal from the control signal as a function of the random

Abstract: The two output currents (INP, IN) which are produced by a current source digital/analog converter (DAC) are supplied to the two halves of a symmetrical transimpedance amplifier. The input current (INP, IN) is supplied to a first stage, which is formed by a first transistor (N2), and a potential at the output of the first stage is supplied to a second stage, which is formed by a second transistor (N3), and the output voltage (VOUT, VOUTP) is formed by a potential at the output of the second stage. The output of the second stage is coupled to the output of the first stage through a Miller capacitor (Cm). The output of the transimpedance amplifier is coupled to its input by means of a connecting line which contains a feedback resistor (Rf).

Abstract: A circuit for setting the operating point of a BGR circuit is disclosed. In the circuit, a voltage comparator (P5, P6, I3) compares the output voltage of an operational amplifier of the BGR circuit with the voltage dropping across an auxiliary circuit branch (R5, D3). The auxiliary circuit branch (R5, D3) resembles the arrangement of a circuit branch (R3, D1) of the BGR circuit, and a current source (P8) generates as a function of the result of the comparison a setting current that is fed into an input of the operational amplifier.

Abstract: The invention relates to a circuit for low noise, fully differential amplification. A feedback signal (121) is detected in a differential output step of the differential amplification circuit by means of a voltage distributor formed by a first feedback resistance (119) and a second feedback resistance (120). A first output signal (111) is provided at a first output circuit node (117) and a second output signal (112) is provided at a second output circuit node (118). The respective first and second output signals (111) or (112) form a full output signal which corresponds to an input signal formed by a first and a second input signal (101) or (102). A load current (134), an input current (132) and a reference current (132) are established by means of a load current source (128), an input current source (131) and a reference current source (127).

Abstract: A circuit for setting the operating point of a BGR circuit is disclosed. In the circuit, a voltage comparator (P5, P6, I3) compares the output voltage of an operational amplifier of the BGR circuit with the voltage dropping across an auxiliary circuit branch (R5, D3). The auxiliary circuit branch (R5, D3) resembles the arrangement of a circuit branch (R3, D1) of the BGR circuit, and a current source (P8) generates as a function of the result of the comparison a setting current that is fed into an input of the operational amplifier.