Abstract: Embodiments provide a mixer cell, which is implemented to logically combine a data signal with an oscillator signal and a sign signal to obtain a mixer cell output signal based on the logical combination. Further embodiments provide a modulator with a plurality of mixer cells.

Abstract: A ring oscillator includes a ring of a plurality of delay elements and a start edge injector for injecting a start edge into the ring. The start edge injector varies an injection point for the start edge in the ring.

Abstract: A differential delay line includes a series connection of a plurality of differential delay stages. Each differential delay stage includes a first delay element and a second delay element. The first delay element has a first input, a second input and an output. The second delay element has a first input, a second input and an output. The output of the first delay element of an n-th differential delay stage of the plurality of differential delay stages is coupled to an input of the second delay element of an (n+m)-th differential delay stage of the plurality of differential delay stages, wherein m is an even natural number larger than or equal to two.

Abstract: One embodiment of the present disclosure relates to a circuit. The circuit includes a digital to analog converter (DAC) configured to convert a time-varying, multi-bit digital value to a corresponding time-varying output current. The circuit also includes a mixer module downstream of the DAC and comprising a plurality of mixers. A control block is configured to selectively steer output current from the DAC to different mixers of the mixer module. Other techniques are also described.

Abstract: One embodiment of the present disclosure relates to a circuit. The circuit includes a digital to analog converter (DAC) configured to convert a time-varying, multi-bit digital value to a corresponding time-varying output current. The circuit also includes a mixer module downstream of the DAC and comprising a plurality of mixers. A control block is configured to selectively steer output current from the DAC to different mixers of the mixer module. Other techniques are also described.

Abstract: An analog-to-digital converter for converting an input signal includes a sigma-delta modulator for receiving an analog modulator input signal and for providing a digital modulator output signal and an interference cancellation loop. The interference cancellation loop includes a digital filter, a digital-to-analog converter, and a signal combiner. The digital filter is configured to amplify the sigma-delta output signal in a frequency band, attenuate the sigma-delta output signal outside the frequency band and a transition band surrounding the frequency band, and provide a filtered digital feedback signal. The digital-to-analog converter is configured to convert the filtered digital signal to a cancellation signal. The signal combiner is configured to combine the input signal with the cancellation signal resulting in the modulator input signal, in order to at least partially cancel interference signal portions within the input signal.

Abstract: A digital-to-analog conversion arrangement for converting a digital input signal comprises first and second digital-to-analog converters (DACs) having different signal resolutions and a digital-to-analog converter selector for selecting the first DAC or the second DAC if the digital input signal has a power in a first or a second power range, respectively. The digital-to-analog conversion arrangement further comprises an analog signal merger for merging a first analog signal and a second analog signal, the first analog signal being based on a first analog output signal of the first digital-to-analog converter and the second analog signal being based on a second analog output signal of the second analog-to-digital converter. A corresponding method for digital-to-analog conversion of a digital input signal and a computer readable digital storage medium are also described.

Abstract: A reference quantity generator for generating a reference quantity includes a reference source configured to provide a reference source signal, a digitally controlled signal source and a digital controller. The digitally controlled signal source is configured to provide a digitally controlled quantity. The reference quantity is determined based on the digitally controlled quantity. The digital controller is configured to provide a digital control signal to control the digitally controlled signal source to adapt the digitally controlled quantity based on the reference source signal using a feedback.

Abstract: One embodiment of the present disclosure relates to a circuit. The circuit includes a digital to analog converter (DAC) configured to convert a time-varying, multi-bit digital value to a corresponding time-varying output current. The circuit also includes a mixer module downstream of the DAC and comprising a plurality of mixers. A control block is configured to selectively steer output current from the DAC to different mixers of the mixer module. Other techniques are also described.

Abstract: Embodiments provide a mixer cell, which is implemented to logically combine a data signal with an oscillator signal and a sign signal to obtain a mixer cell output signal based on the logical combination. Further embodiments provide a modulator with a plurality of mixer cells.

Abstract: A digital-to-analog conversion arrangement for converting a digital input signal comprises first and second digital-to-analog converters (DACs) having different signal resolutions and a digital-to-analog converter selector for selecting the first DAC or the second DAC if the digital input signal has a power in a first or a second power range, respectively. The digital-to-analog conversion arrangement further comprises an analog signal merger for merging a first analog signal and a second analog signal, the first analog signal being based on a first analog output signal of the first digital-to-analog converter and the second analog signal being based on a second analog output signal of the second analog-to-digital converter. A corresponding method for digital-to-analog conversion of a digital input signal and a computer readable digital storage medium are also described.

Abstract: This disclosure is directed towards techniques and methods of suppressing the effect of modulated clock jitter in a digital to analog conversion (DAC) circuit of a polar modulator in a transceiver. A phase locked loop (PLL) in a modulator circuit may introduce a deterministic jitter in DAC generated pulses which may lead to amplitude variations in the DAC generated pulses. The clock jitter may change the duty cycle of the input amplitude to the DAC which may result in a variation of the output of the DAC generated pulse. A digital pre-distortion or digital multiplier circuit may be introduced before the DAC circuit to increase or decrease the DAC amplitude to compensate for the pulse width modulation.

Abstract: In one implementation, a polar transmitter includes a digital signal processing component that processes baseband signals and provides a baseband data signal with amplitude values; and a digital pre-distortion component that receives the baseband data signal with amplitude values, compensates for jitter error in the baseband data signal with amplitude values, and provides an adjusted modulated signal.

Abstract: This disclosure relates to clock jitter suppression in digital to analog converter generated pulses for a polar transmitter.

Abstract: An amplifier circuit is disclosed having an output transistor for driving a complex load over a drive frequency range, wherein in the lower part of the range an inductive component of the load dominates and in the upper part the inductive component does not dominate. The amplifier circuit includes a current mirror circuit that is connected upstream of the output transistor and has a shunt path to a second potential, for the purpose of relatively reducing a DC current flowing through the output transistor in comparison with an AC current flowing through the latter.

Abstract: An amplifier circuit is disclosed having an output transistor for driving a complex load over a drive frequency range, wherein in the lower part of the range an inductive component of the load dominates and in the upper part the inductive component does not dominate. The amplifier circuit includes a current mirror circuit that is connected upstream of the output transistor and has a shunt path to a second potential, for the purpose of relatively reducing a DC current flowing through the output transistor in comparison with an AC current flowing through the latter.

Abstract: This disclosure relates to monitoring the output of one or more amplifying structures and providing an auxiliary input signal under certain conditions.

Abstract: In one embodiment, an amplifier arrangement includes an amplifier having a first input, a second input and an output, a first resistor network, having a first parallel circuit formed by a first number N of resistors, and a second resistor network, having a first resistor or a second parallel circuit formed by a second number M of resistors. The resistors of the first and second resistor networks each have approximately the same nominal value, an approximately identical width W and an approximately identical length L of a resistive layer. The first and second resistor networks are coupled to the amplifier.

Abstract: The two output currents (INP, IN) which are produced by a current source digital/analog converter (DAC) are supplied to the two halves of a symmetrical transimpedance amplifier. The input current (INP, IN) is supplied to a first stage, which is formed by a first transistor (N2), and a potential at the output of the first stage is supplied to a second stage, which is formed by a second transistor (N3), and the output voltage (VOUT, VOUTP) is formed by a potential at the output of the second stage. The output of the second stage is coupled to the output of the first stage through a Miller capacitor (Cm). The output of the transimpedance amplifier is coupled to its input by means of a connecting line which contains a feedback resistor (Rf).

Abstract: The control apparatus (8?) is used to dynamically assign N individual references to N individual comparators of a quantizer in a sigma-delta analogue/digital converter, the control apparatus (8?) generating a digital control signal (9?). The control apparatus (8?) has a storage means (12) for providing the value of the control signal (9?) at the time k?1, and a summation means (10) for summing the output signal Y of the quantizer with the stored value of the first control signal (9?) at the time k?1.