Abstract: The invention relates to a hair styling device, and in particular a multifunctional hair styling device having components which can carry out a number of different (and distinct) styling operations. The invention provides a hair styling device having a body portion and a handle portion, the body portion having an air inlet and an air outlet, an impeller between the air inlet and the air outlet and an electric motor to rotate the impeller, the handle portion having a pair of heating panels. The handle portion is separable from the body portion and can be used alone as a hair straighter, or the device can be used as a hair dryer with the handle portion attached to the body portion. The body portion can optionally include a hair curling chamber adapted for hair curling.

Abstract: A semiconductor device includes a fin protruding upwardly from a substrate. The fin includes a first sidewall and an opposing second sidewall and a top surface extending between the first and second sidewalls. The semiconductor device also includes a two-dimensional material layer disposed on the first and second sidewalls of the fin without being disposed on the top surface of the fin, and a gate stack disposed on the fin. The gate stack contacts a channel region defined in the two-dimensional material layer. The two-dimensional material layer includes a flat portion extending laterally away from the fin.

Abstract: This invention relates to a hair styling device, a hair styling method, and a drive system suitable for use in the hair styling device. The invention relates in particular to a hair styling device (10; 210) for imparting a wave to a section of hair (36) without clamping the section of hair in the wave form. The device has a first forming member (24) and a second forming member (24) with a hair-receiving region (38) between the forming members. A driving member (20; 120) is movable relative to the first forming member and the second forming member to deform the section of hair in the hair-receiving region.

Abstract: A crystalline channel layer of a semiconductor material is formed in a backend process over a crystalline dielectric seed layer. A crystalline magnesium oxide MgO is formed over an amorphous inter-layer dielectric layer. The crystalline MgO provides physical link to the formation of a crystalline semiconductor layer thereover.

Abstract: A field effect transistor includes a channel made of germanium and a source/drain portion. The source/drain portion includes a germanium layer, an interfacial epitaxial layer over the germanium layer, a semiconductor layer over the interfacial epitaxial layer, and a conducting layer over the semiconductor layer. The interfacial epitaxial layer contains germanium and an element from the semiconductor layer and has a thickness in a range from about 1 nm to about 3 nm.

Abstract: In an embodiment, a device includes: a semiconductor substrate having a channel region; a gate stack over the channel region; and an epitaxial source/drain region adjacent the gate stack, the epitaxial source/drain region including: a main portion in the semiconductor substrate, the main portion including a semiconductor material doped with gallium, a first concentration of gallium in the main portion being less than the solid solubility of gallium in the semiconductor material; and a finishing portion over the main portion, the finishing portion doped with gallium, a second concentration of gallium in the finishing portion being greater than the solid solubility of gallium in the semiconductor

Abstract: Various methods for fabricating non-planar integrated circuit devices, such as FinFET devices, are disclosed herein. An exemplary method includes forming a rib structure extending from a substrate; forming a two-dimensional material layer (including, for example, transition metal dichalcogenide or graphene) on the rib structure and the substrate; patterning the two-dimensional material layer, such that the two-dimensional material layer is disposed on at least one surface of the rib structure; and forming a gate on the two-dimensional material layer. In some implementations, a channel region, a source region, and a drain region are defined in the two-dimensional material layer. The channel region is disposed between the source region and the drain region, where the gate is disposed over the channel region. In some implementations, the patterning includes removing the two-dimensional material layer disposed on a top surface of the substrate and/or disposed on a top surface of the rib structure.

Abstract: A method of forming a semiconductor device includes forming source/drain contact openings extending through at least one dielectric layer to expose source/drain contact regions of source/drain structures. The method further includes forming conductive plugs in the source/drain contact openings. The method further includes depositing a light blocking layer over the conductive plugs and the at least one dielectric layer. The method further includes etching the light blocking layer to expose the conductive plugs. The method further includes directing a laser irradiation to the conductive plugs and the light blocking layer. The laser irradiation is configured to activate dopants in the source/drain contact regions.

Abstract: In an embodiment, a device includes: a semiconductor substrate having a channel region; a gate stack over the channel region; and an epitaxial source/drain region adjacent the gate stack, the epitaxial source/drain region including: a main portion in the semiconductor substrate, the main portion including a semiconductor material doped with gallium, a first concentration of gallium in the main portion being less than the solid solubility of gallium in the semiconductor material; and a finishing portion over the main portion, the finishing portion doped with gallium, a second concentration of gallium in the finishing portion being greater than the solid solubility of gallium in the semiconductor material.

Abstract: A semiconductor structure includes a substrate, a first epitaxial layer, a second epitaxial layer, and a transistor. The substrate includes a first pyramid protrusion, a second pyramid protrusion, a third pyramid protrusion, and a fourth pyramid protrusion. The first and second pyramid protrusions are arranged along a first direction, the second and fourth pyramid protrusions are arranged along the first direction, and the first and third pyramid protrusions are arranged along a second direction crossing the first direction. The first epitaxial layer is over the substrate and in contact with the first, second, third, and fourth pyramid protrusions. The second epitaxial layer is over the first epitaxial layer. The transistor is over the second epitaxial layer.

Abstract: A semiconductor device is provided. The semiconductor device includes a template layer disposed over a substrate and having a trench therein, a buffer structure disposed over a bottom surface of the trench and comprising a metal oxide, a single crystal semiconductor structure disposed within the trench and over the buffer structure and a gate structure disposed over a channel region of the single crystal semiconductor structure.

Abstract: A method of forming a semiconductor device includes forming source/drain contact openings extending through at least one dielectric layer to expose source/drain contact regions of source/drain structures. The method further includes depositing a light blocking layer along sidewalls and bottom surfaces of the source/drain contact openings and a topmost surface of the at least one dielectric layer. The method further includes performing a laser annealing process to activate dopants in the source/drain contact region. The method further includes forming source/drain contact structures within source/drain contact openings.

Abstract: In a method of manufacturing a semiconductor device, an opening is formed in an interlayer dielectric layer such that a source/drain region is exposed in the opening. A first semiconductor layer is formed to fully cover the exposed source/drain region within the opening. A heating process is performed to make an upper surface of the first semiconductor layer substantially flat. A conductive contact layer is formed over the first semiconductor layer.

Abstract: In a method of manufacturing a semiconductor device, an opening is formed in an interlayer dielectric layer such that a source/drain region is exposed in the opening. A first semiconductor layer is formed to fully cover the exposed source/drain region within the opening. A heating process is performed to make an upper surface of the first semiconductor layer substantially flat. A conductive contact layer is formed over the first semiconductor layer.

Abstract: Metal nitride diffusion barriers may be included between cobalt-based structures and ruthenium-based structures to reduce, minimize, and/or prevent intermixing of cobalt into ruthenium. A metal nitride diffusion barrier layer may include a cobalt nitride (CoNx), a ruthenium nitride (RuNx), or another metal nitride that has a bond dissociation energy greater than the bond dissociation energy of cobalt to cobalt (Co—Co), and may therefore function as a strong barrier to cobalt migration and diffusion into ruthenium. Moreover, cobalt nitride and ruthenium nitride have lower resistivity relative to other materials such as titanium nitride (TiN), tungsten nitride (WN), and tantalum nitride (TaN). In this way, the metal nitride diffusion barriers are capable of minimizing cobalt diffusion and intermixing into ruthenium-based interconnect structures while maintaining a low contact resistance for the interconnect structures.

Abstract: In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a channel region of a semiconductor layer, a source/drain epitaxial layer is formed on opposing sides of the dummy gate structure, a planarization operation is performed on the source/drain epitaxial layer, the planarized source/drain epitaxial layer is patterned, the dummy gate structure is removed to form a gate space, and a metal gate structure is formed in the gate space.

Abstract: A semiconductor device is provided. The semiconductor device includes a template layer disposed over a substrate and having a trench therein, a buffer structure disposed over a bottom surface of the trench and comprising a metal oxide, a single crystal semiconductor structure disposed within the trench and over the buffer structure and a gate structure disposed over a channel region of the single crystal semiconductor structure.

Abstract: In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a channel region of a semiconductor layer, a source/drain epitaxial layer is formed on opposing sides of the dummy gate structure, a planarization operation is performed on the source/drain epitaxial layer, the planarized source/drain epitaxial layer is patterned, the dummy gate structure is removed to form a gate space, and a metal gate structure is formed in the gate space.

Abstract: Provided herein are semiconductor structures that include germanium and have a germanium nitride layer on the surface, as well as methods of forming the same. The described structures include nanowires and fins. Methods of the disclosure include metal-organic chemical vapor deposition with a germanium precursor. The described methods also include using a N2H4 vapor.

Abstract: A crystalline channel layer of a semiconductor material is formed in a backend process over a crystalline dielectric seed layer. A crystalline magnesium oxide MgO is formed over an amorphous inter-layer dielectric layer. The crystalline MgO provides physical link to the formation of a crystalline semiconductor layer thereover.