Abstract: According to one example, a method includes epitaxially growing first portions of a plurality of elongated semiconductor structures on a semiconductor substrate, the elongated semiconductor structures running perpendicular to the substrate. The method further includes forming a gate layer on the substrate, the gate layer contacting the elongated semiconductor structures. The method further includes performing a planarization process on the gate layer and the elongated semiconductor structures, and epitaxially growing second portions of the plurality of elongated semiconductor structures, the second portions comprising a different material than the first portions.

Abstract: Various heterostructures and methods of forming heterostructures are disclosed. A method includes removing portions of a substrate to form a temporary fin protruding above the substrate, forming a dielectric material over the substrate and over the temporary fin, removing the temporary fin to form a trench in the dielectric material, the trench exposing a portion of a first crystalline material of the substrate, forming a template material at least partially in the trench, the template material being a second crystalline material that is lattice mismatched to the first crystalline material, forming a barrier material over the template material, the barrier material being a third crystalline material, forming a device material over the barrier material, the device material being a fourth crystalline material, forming a gate stack over the device material, and forming a first source/drain region and a second source/drain region in the device material.

Abstract: A semiconductor device includes a plurality of fins. Each of the fins has a multi-layer stack comprising a first nanowire and a second nanowire. A first portion of the first nanowire and second nanowire are doped to form source and drain regions. An epitaxial layer wraps around the first portion of first nanowire and second nanowire over the source and drain region. A gate is disposed over a second portion of the first nanowire and second nanowire. The epitaxial layer is interposed in between the first nanowire and the second nanowire over the source and drain region. The epitaxial layer has a zig-zag contour.

Abstract: According to one example, a method includes epitaxially growing first portions of a plurality of elongated semiconductor structures on a semiconductor substrate, the elongated semiconductor structures running perpendicular to the substrate. The method further includes forming a gate layer on the substrate, the gate layer contacting the elongated semiconductor structures. The method further includes performing a planarization process on the gate layer and the elongated semiconductor structures, and epitaxially growing second portions of the plurality of elongated semiconductor structures, the second portions comprising a different material than the first portions.

Abstract: A semiconductor device includes a substrate, a gate structure, a plurality of nanowires, a sacrificial material, and an epitaxy structure. The gate structure is disposed on and in contact with the substrate. The nanowires extend through the gate structure. The sacrificial material is separated from the gate structure. The epitaxy structure is in contact with the nanowires, is separated from the substrate, and surrounds the sacrificial material.

Abstract: A gate-all-around field effect transistor (GAA FET) includes an InAs nano-wire as a channel layer, a gate dielectric layer wrapping the InAs nano-wire, and a gate electrode metal layer formed on the gate dielectric layer. The InAs nano-wire has first to fourth major surfaces three convex-rounded corner surfaces and one concave-rounded corner surface.

Abstract: Provided is a method of forming a nanowire-based device. The method includes forming a first mask layer over a substrate; forming a first opening in the first mask layer; growing a first nanowire that protrudes through the first opening in the first mask layer, wherein the first nanowire has a first diameter; removing the first mask layer; oxidizing a sidewall of the first nanowire; etching the oxidized sidewall of the first nanowire; forming a second mask layer overlaying the substrate; removing the first nanowire thereby forming a second opening in the second mask layer; and growing a second nanowire that protrudes through the second opening in the second mask layer, wherein the second nanowire has a second diameter and the second diameter is different than the first diameter.

Abstract: Semiconductor devices and fin field effect transistors (FinFETs) are disclosed. In some embodiments, a representative semiconductor device includes a group III material over a substrate, the group III material comprising a thickness of about 2 monolayers or less, and a group III-V material over the group III material.

Abstract: In a method of forming a Group III-V semiconductor layer on a Si substrate, a first source gas containing a Group V element is supplied to a surface of the Si substrate while heating the substrate at a first temperature, thereby terminating the Si surface with the Group V element. Then, a second source gas containing a Group III element is supplied to the surface while heating the substrate at a second temperature, thereby forming a nucleation layer directly on the surface of the Si substrate. After the nucleation layer is formed, the supply of the second source gas is stopped and the substrate is annealed at a third temperature while the first source gas being supplied, thereby foaming a seed layer. After the annealing, the second source gas is supplied while heating the substrate at a fourth temperature, thereby forming a body III-V layer semiconductor on the seed layer.

Abstract: A method includes depositing an insulating layer over a substrate, the substrate including a first semiconductor material. The method also includes forming an opening in the insulating layer, the opening exposing a surface of the substrate. The method also includes growing a nanowire over the exposed surface of the substrate, the nanowire extending out of the opening away from the substrate, the nanowire including a second semiconductor material different from the first semiconductor material. The method also includes laterally growing the second semiconductor material on exposed sidewalls of the nanowire.

Abstract: A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a third type region including a third conductivity type that is opposite the first conductivity type, the third type region covering the first type region. The semiconductor device includes a fourth type region including a fourth conductivity type that is opposite the second conductivity type, the fourth type region covering the second type region. The semiconductor device includes a channel region extending between the third type region and the fourth type region.

Abstract: In a method of forming a Group III-V semiconductor layer on a Si substrate, a first source gas containing a Group V element is supplied to a surface of the Si substrate while heating the substrate at a first temperature, thereby terminating the Si surface with the Group V element. Then, a second source gas containing a Group III element is supplied to the surface while heating the substrate at a second temperature, thereby forming a nucleation layer directly on the surface of the Si substrate. After the nucleation layer is formed, the supply of the second source gas is stopped and the substrate is annealed at a third temperature while the first source gas being supplied, thereby forming a seed layer. After the annealing, the second source gas is supplied while heating the substrate at a fourth temperature, thereby forming a body III-V layer semiconductor on the seed layer.

Abstract: Semiconductor devices and fin field effect transistors (FinFETs) are disclosed. In some embodiments, a representative semiconductor device includes a group III material over a substrate, the group III material comprising a thickness of about 2 monolayers or less, and a group III-V material over the group III material.

Abstract: Various methods for fabricating non-planar integrated circuit devices, such as FinFET devices, are disclosed herein. An exemplary method includes forming a rib structure extending from a substrate; forming a two-dimensional material layer (including, for example, transition metal dichalcogenide or graphene) on the rib structure and the substrate; patterning the two-dimensional material layer, such that the two-dimensional material layer is disposed on at least one surface of the rib structure; and forming a gate on the two-dimensional material layer. In some implementations, a channel region, a source region, and a drain region are defined in the two-dimensional material layer. The channel region is disposed between the source region and the drain region, where the gate is disposed over the channel region. In some implementations, the patterning includes removing the two-dimensional material layer disposed on a top surface of the substrate and/or disposed on a top surface of the rib structure.

Abstract: A fin field effect transistor (FinFET) device includes a substrate and a template material over the substrate. The template material absorbs lattice mismatches with the substrate. The FinFET device also includes a barrier material over the template material. The barrier material is free of point defects. The FinFET device further includes a channel material over the barrier material.

Abstract: Semiconductor devices and methods of forming the same are provided. A template layer is formed on a substrate, the template layer having a recess therein. A plurality of nanowires is formed in the recess. A gate stack is formed over the substrate, the gate stack surrounding the plurality of nanowires.

Abstract: Provided is a method of forming a nanowire-based device. The method includes forming a first mask layer over a substrate; forming a first opening in the first mask layer; growing a first nanowire that protrudes through the first opening in the first mask layer, wherein the first nanowire has a first diameter; removing the first mask layer; oxidizing a sidewall of the first nanowire; etching the oxidized sidewall of the first nanowire; forming a second mask layer overlaying the substrate; removing the first nanowire thereby forming a second opening in the second mask layer; and growing a second nanowire that protrudes through the second opening in the second mask layer, wherein the second nanowire has a second diameter and the second diameter is different than the first diameter.

Abstract: A thin-sheet non-planar circuit device such as a FinFET and a method for forming the device is disclosed. In some exemplary embodiments, the device includes a substrate having a top surface and a feature disposed on the substrate that extends above the top surface. A material layer disposed on the feature. The material layer includes a plurality of source/drain regions and a channel region disposed between the source/drain regions. A gate stack is disposed on the channel region of the material layer. In some such embodiments, the feature includes a plurality of side surfaces, and the material layer is disposed on each of the side surface surfaces. In some such embodiments, the feature also includes a top surface and the material layer is further disposed on the top surface. In some embodiments, the top surface of the feature is free of the material layer.

Abstract: Provided is a method of forming a nanowire-based device. The method includes forming a mask layer over a substrate; forming an opening in the mask layer; growing an arsenic-based nanowire from the substrate that extends through the opening; removing the mask layer; forming a phosphorus-based layer over the arsenic-based nanowire; and removing the phosphorus-based layer.

Abstract: A method includes depositing an insulating layer over a substrate, the substrate including a first semiconductor material. The method also includes forming an opening in the insulating layer, the opening exposing a surface of the substrate. The method also includes growing a nanowire over the exposed surface of the substrate, the nanowire extending out of the opening away from the substrate, the nanowire including a second semiconductor material different from the first semiconductor material. The method also includes laterally growing the second semiconductor material on exposed sidewalls of the nanowire.