Abstract: Provided is a method of forming a nanowire-based device. The method includes forming a first mask layer over a substrate; forming a first opening in the first mask layer; growing a first nanowire that protrudes through the first opening in the first mask layer, wherein the first nanowire has a first diameter; removing the first mask layer; oxidizing a sidewall of the first nanowire; etching the oxidized sidewall of the first nanowire; forming a second mask layer overlaying the substrate; removing the first nanowire thereby forming a second opening in the second mask layer; and growing a second nanowire that protrudes through the second opening in the second mask layer, wherein the second nanowire has a second diameter and the second diameter is different than the first diameter.

Abstract: Provided is a method of forming a nanowire-based device. The method includes forming a first mask layer over a substrate; forming a first opening in the first mask layer; growing a first nanowire that protrudes through the first opening in the first mask layer, wherein the first nanowire has a first diameter; removing the first mask layer; oxidizing a sidewall of the first nanowire; etching the oxidized sidewall of the first nanowire; forming a second mask layer overlaying the substrate; removing the first nanowire thereby forming a second opening in the second mask layer; and growing a second nanowire that protrudes through the second opening in the second mask layer, wherein the second nanowire has a second diameter and the second diameter is different than the first diameter.

Abstract: According to one example, a method includes epitaxially growing first portions of a plurality of elongated semiconductor structures on a semiconductor substrate, the elongated semiconductor structures running perpendicular to the substrate. The method further includes forming a gate layer on the substrate, the gate layer contacting the elongated semiconductor structures. The method further includes performing a planarization process on the gate layer and the elongated semiconductor structures, and epitaxially growing second portions of the plurality of elongated semiconductor structures, the second portions comprising a different material than the first portions.

Abstract: Provided is a method of forming a nanowire-based device. The method includes forming a mask layer over a substrate; forming an opening in the mask layer; growing an arsenic-based nanowire from the substrate that extends through the opening; removing the mask layer; forming a phosphorus-based layer over the arsenic-based nanowire; and removing the phosphorus-based layer.

Abstract: A method of providing an out-of-plane semiconductor structure and a structure fabricated thereby is disclosed. The method comprises acts of: providing a substrate defining a major surface; providing a template layer having a predetermined template thickness on the major surface of the substrate; forming a recess in the template layer having a recess pattern and a recess depth smaller than the template thickness; and epitaxially growing a semiconductor structure from the recess. A planar shape of the recess pattern formed in the template layer substantially dictates an extending direction of the semiconductor structure.

Abstract: Semiconductor devices and methods of forming the same are provided. A template layer is formed on a substrate, the template layer having a recess therein. A plurality of nanowires is formed in the recess. A gate stack is formed over the substrate, the gate stack surrounding the plurality of nanowires.

Abstract: A method of manufacturing a semiconductor device may include: forming an opening in an insulating layer to expose a portion of a major surface of a substrate, the substrate comprising a first semiconductor material; forming a protrusion in the opening using a first epitaxial growth process, the protrusion comprising a first portion disposed in the opening and a second portion extending out of the opening, the protrusion comprising a second semiconductor material different from the first semiconductor material; and forming the second semiconductor material on sidewalls of the second portion of the protrusion using a second epitaxial growth process different from the first epitaxial growth process.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a first material layer over a substrate. The first material layer has a sidewall defining a first opening, wherein the first opening has a first shape. The method also includes forming a sacrificial feature within the first opening and the sacrificial feature has a second shape, which is different than the first shape such that there is a cavity between an edge of the sacrificial feature and the sidewall of the first material layer. The method also includes filling in cavity with a second material layer, removing the sacrificial feature to form a second opening, filling in the second opening with a third material layer, removing the second material layer to reveal the cavity and forming a conductive feature within the cavity.

Abstract: A method of fabricating a nanowire array is disclosed. The method includes forming a mask layer over a substrate, wherein the mask layer includes a plurality of openings; growing a first plurality of nanowires through the plurality of openings; forming a conformal layer over the first plurality of nanowires and the mask layer; planarizing the conformal layer over the first plurality of nanowires to form a coplanar top surface defined by the first plurality of nanowires and the conformal layer; removing a portion of the conformal layer and a portion of the mask layer to expose the substrate, wherein the portions of the conformal layer and the mask layer are located between adjacent nanowires from the plurality of nanowires; and growing a second plurality of nanowires on the exposed substrate.

Abstract: Semiconductor devices and methods of forming the same are provided. A template layer is formed on a substrate, the template layer having a recess therein. A plurality of nanowires is formed in the recess. A gate stack is formed over the substrate, the gate stack surrounding the plurality of nanowires.

Abstract: An apparatus comprises a first semiconductor fin, a second semiconductor fin and a third semiconductor fin over a substrate, wherein the first semiconductor fin and the second semiconductor fin are separated by a first isolation region and the second semiconductor fin and the third semiconductor fin are separated by a second isolation region, and wherein a width of the first isolation region is greater than a width of the second isolation region.

Abstract: A method of manufacturing a semiconductor device may include: forming an opening in an insulating layer to expose a portion of a major surface of a substrate, the substrate comprising a first semiconductor material; forming a protrusion in the opening using a first epitaxial growth process, the protrusion comprising a first portion disposed in the opening and a second portion extending out of the opening, the protrusion comprising a second semiconductor material different from the first semiconductor material; and forming the second semiconductor material on sidewalls of the second portion of the protrusion using a second epitaxial growth process different from the first epitaxial growth process.

Abstract: Various heterostructures and methods of forming heterostructures are disclosed. A method includes removing portions of a substrate to form a temporary fin protruding above the substrate, forming a dielectric material over the substrate and over the temporary fin, removing the temporary fin to form a trench in the dielectric material, the trench exposing a portion of a first crystalline material of the substrate, forming a template material at least partially in the trench, the template material being a second crystalline material that is lattice mismatched to the first crystalline material, forming a barrier material over the template material, the barrier material being a third crystalline material, forming a device material over the barrier material, the device material being a fourth crystalline material, forming a gate stack over the device material, and forming a first source/drain region and a second source/drain region in the device material.

Abstract: A method comprises providing a substrate formed of a first semiconductor material, wherein the substrate comprises a plurality of isolation regions, etching away upper portions of the substrate to form a plurality of trenches, wherein each trench is between two adjacent isolation regions, over-growing a plurality of semiconductor fins in the trenches over the substrate through an epitaxial growth process, wherein upper portions of the semiconductor fins are above top surfaces of the isolation regions, applying a planarization process to the semiconductor fins, wherein top surfaces of the semiconductor fins are level with top surfaces of the isolation regions as a result of performing the step of applying the planarization process and removing a defect semiconductor fin to form a vacant trench.

Abstract: Semiconductor devices and methods of forming the same are provided. A template layer is formed on a substrate, the template layer having a recess therein. A plurality of nanowires is formed in the recess. A gate stack is formed over the substrate, the gate stack surrounding the plurality of nanowires.

Abstract: A method comprises providing a substrate formed of a first semiconductor material, wherein the substrate comprises a plurality of isolation regions, etching away upper portions of the substrate to form a plurality of trenches, wherein each trench is between two adjacent isolation regions, over-growing a plurality of semiconductor fins in the trenches over the substrate through an epitaxial growth process, wherein upper portions of the semiconductor fins are above top surfaces of the isolation regions, applying a planarization process to the semiconductor fins, wherein top surfaces of the semiconductor fins are level with top surfaces of the isolation regions as a result of performing the step of applying the planarization process and removing a defect semiconductor fin to form a vacant trench.

Abstract: A FinFET with backside passivation layer comprises a template layer disposed on a substrate, a buffer layer disposed over the template layer, a channel backside passivation layer disposed over the buffer layer and a channel layer disposed over the channel backside passivation layer. A gate insulator layer is disposed over and in contact with the channel layer and the channel backside passivation layer. The buffer layer optionally comprises aluminum and the channel layer may optionally comprise a III-V semiconductor compound. STIs may be disposed on opposite sides of the channel backside passivation layer, and the channel backside passivation layer may have a top surface disposed above the top surface of the STIs and a bottom surface disposed below the top surface of the STIs.

Abstract: A fin field effect transistor (FinFET) device includes a substrate and a template material over the substrate. The template material absorbs lattice mismatches with the substrate. The FinFET device also includes a barrier material over the template material. The barrier material is free of point defects. The FinFET device further includes a channel material over the barrier material.

Abstract: Various heterostructures and methods of forming heterostructures are disclosed. A structure includes a substrate, a template layer, a barrier layer, and a device layer. The substrate comprises a first crystalline material. The template layer comprises a second crystalline material, and the second crystalline material is lattice mismatched to the first crystalline material. The template layer is over and adjoins the first crystalline material, and the template layer is at least partially disposed in an opening of a dielectric material. The barrier layer comprises a third crystalline material, and the third crystalline material is a binary III-V compound semiconductor. The barrier layer is over the template layer. The device layer comprises a fourth crystalline material, and the device layer is over the barrier layer.

Abstract: A method comprises growing a channel layer comprising a first channel region and a second channel region, depositing a first hard mask layer over the channel layer, patterning the first hard mask layer, applying a first delta doping process to the first channel region to form a first delta doping layer over the first channel region, depositing a first cap layer over the first delta doping layer, depositing a second hard mask layer over the channel layer, wherein the first cap layer is embedded in the second hard mask layer, patterning the second hard mask layer and the first hard mask layer to expose the second channel region, applying a second delta doping process to the second channel region to form a second delta doping layer over the second channel region and applying a first diffusion process to the first delta doping layer and the second delta doping layer.