Abstract: A device for trapping ions includes: a substrate having a metal layer structure; and at least one ion trap configured to trap ions in a space over the substrate. The metal layer structure is a multi-layer metal structure that includes: a top metal layer having one or more electrodes forming part of the at least one ion trap; a redistribution metal layer having wiring for connecting the one or more electrodes; a first insulating layer arranged between the top metal layer and the redistribution layer and having one or more voids; and one or more connection elements arranged in the one or more voids that connect the wiring from the redistribution metal layer with the one or more electrodes in the top metal layer.

Abstract: A resistance spot welded joint of at least two steel sheets and a method of producing a resistance spot welded joint of at least two steel sheets, wherein at least one of the steel sheets is provided with a Zn containing layer, the steel sheet has a tensile strength of at least 980 MPa, a multiphase microstructure comprising bainite, bainitic ferrite and tempered martensite in a total amount of at least of 75 volume % and retained austenite in an amount of 3-20 volume % and wherein the steel sheet provided with the Zn containing layer has a composition consisting of (in wt. %): C 0.1-0.3; Si 0.2-3.0; Mn 1.0-3.0; Cr?2.0; Mo?0.5; Al?2.0; Nb?0.2; V?0.2; Ti 0.01-0.15; B 0.0005-0.01; and balance Fe apart from impurities, wherein the heat affected zone in the spot welded joint is free from cracks having a length of more than 500 ?m.

Abstract: An electronic module includes a semiconductor package, and a clip connected to the semiconductor package. The clip is connected to or includes at least one fastening element which is configured to make a connection to an external heatsink.

Abstract: A semiconductor package is provided. The semiconductor package may include at least one semiconductor chip including a contact pad configured to conduct a current, a conductor element, wherein the conductor element is arranged laterally overlapping the contact pad and with a distance to the contact pad, at least one electrically conductive spacer, a first adhesive system configured to electrically and mechanically connect the at least one electrically conductive spacer with the contact pad, and a second adhesive system configured to electrically and mechanically connect the at least one electrically conductive spacer with the conductor element, wherein the conductor element is electrically conductively connected to a clip or is at least part of a clip, and wherein the spacer is configured to electrically conductively connect the contact pad with the laterally overlapping portion of the conductor element.

Abstract: A package includes a carrier, an electronic component on the carrier, an encapsulant encapsulating at least part of the carrier and the electronic component, and at least one lead extending beyond the encapsulant and having a punched surface, wherein at least part of at least one side flank of the encapsulant has a sawn texture.

Abstract: An electronic module includes a semiconductor package, and a clip connected to the semiconductor package. The clip is connected to or includes at least one fastening element which is configured to make a connection to an external heat sink.

Abstract: A device includes an interposer including an insulative layer between a lower metal layer and a first upper metal layer and a second upper metal layer, a semiconductor transistor die attached to the first upper metal layer and comprising a first lower main face and a second upper main face, with a drain or collector pad on the first main face and electrically connected to the first upper metal layer, a source or emitter electrode pad and a gate electrode pad on the second main face, a leadframe connected to the interposer and comprising a first lead connected with the first upper metal layer, a second lead connected with the source electrode pad, and a third lead connected with the second upper metal layer, and wherein an electrical connector that is connected between the gate electrode pad and the second upper metal layer is orthogonal to a first electrical connector.

Abstract: A package includes a carrier, an electronic component on the carrier, an encapsulant encapsulating at least part of the carrier and the electronic component, and at least one lead extending beyond the encapsulant and having a punched surface, wherein at least part of at least one side flank of the encapsulant has a sawn texture.

Abstract: A semiconductor package is disclosed. In one example, the package includes a non-power chip including a first electrical contact arranged at a first main surface of the non-power chip. The semiconductor package further includes a power chip comprising a second electrical contact arranged at a second main surface of the power chip. A first electrical redistribution layer coupled to the first electrical contact and a second electrical redistribution layer coupled to the second electrical contact. When measured in a first direction vertical to at least one of the first main surface or the second main surface, a maximum thickness of at least a section of the first electrical redistribution layer is smaller than a maximum thickness of the second electrical redistribution layer.

Abstract: A method includes providing a first lead frame that includes a first die pad and a first row of leads, providing a connection lug, mounting a first semiconductor die on the first die pad, the first semiconductor die including first and second voltage blocking terminals, electrically connecting the connection lug to one of the first and second voltage blocking terminals, electrically connecting a first one of the leads from the first row to an opposite one of the first and second voltage blocking terminals, and forming an encapsulant body of electrically insulating material that encapsulates first die pad and the first semiconductor die. After forming the encapsulant body, the first row of leads each protrude out of a first outer face of the encapsulant body and the connection lug protrudes out of a second outer face of the encapsulant body.

Abstract: A semiconductor device module includes a package carrier having an opening, wherein in the opening there is disposed a semiconductor package including a semiconductor die, an encapsulant, and first vertical contacts, wherein the encapsulant at least partially covers the semiconductor die, and the first vertical contacts are connected to the semiconductor die and extend at least partially through the encapsulant, and a first outer metallic contact layer electrically connected to the first vertical contacts.

Abstract: A method for fabricating a semiconductor device includes: providing a die carrier; disposing a semiconductor die on a main face of the die carrier, the semiconductor die having one or more contact pads; applying an encapsulant at least partially to the semiconductor die and at least a portion of the main face of the die carrier; applying an insulation layer to the encapsulant; and fabricating electrical interconnects by forming openings into the encapsulant and the insulation layer and filling a conductive material into the openings. Additional methods for fabricating a semiconductor device are described.

Abstract: A cold roll strip or sheet includes in (wt %) C 0.08-0.28; Mn 1.4-4.5; Cr 0.01-0.5; Si 0.01-2.5; Al 0.01-0.6; Si+Al?0.1; Si+Al+Cr?0.4; Nb?0.008; Ti?0.02; Mo?0.08; Ca?0.005; V?0.02; balance Fe apart from impurities. The steel is within the area defined by the coordinates A, B, C, D, where Ri/t (y-axle) is plotted vs TS(MPa)/YR (x-axle), and where A is [1200, 2), B is [2000, 4], C is [2000, 3], and D is [1200, 1].

Abstract: A cold roll strip or sheet includes in (wt %): C 0.12-0.20; Mn 1.9-2.6; Cr 0.15-0.3; Si 0.3-0.8; Al 0.8-1.2; Mn+Cr 1.8-5; Nb?0.008; Ti?0.02; Mo?0.08; Ca?0.005; V?0.02; and balance Fe apart from impurities. The steel is within the area defined by the coordinates A, B, C, D, where Ri/t (y-axle) is plotted vs TS (MPa)/YR (x-axle), and where A is [2200, 3.5], B is [2600, 4.5], C is [2600, 3], and D is [2200, 2].

Abstract: A device for trapping ions includes: a substrate having a metal layer structure; and at least one ion trap configured to trap ions in a space over the substrate. The metal layer structure is a multi-layer metal structure that includes: a top metal layer having one or more electrodes forming part of the at least one ion trap; a redistribution metal layer having wiring for connecting the one or more electrodes; a first insulating layer arranged between the top metal layer and the redistribution layer and having one or more voids; and one or more connection elements arranged in the one or more voids that connect the wiring from the redistribution metal layer with the one or more electrodes in the top metal layer.

Abstract: An electronic module includes a semiconductor package including a die carrier, a semiconductor transistor die disposed on the die carrier, an electrical conductor connected to the semiconductor die, and an encapsulant covering the die carrier, the semiconductor die, and the electrical conductor so that a portion of the electrical conductor extends to the outside of the encapsulant. The electronic module further includes an interposer layer on which the semiconductor package is disposed, and a heat sink through which a cooling medium can flow. The interposer layer is disposed on the heatsink.

Abstract: A method of fabricating a semiconductor device package includes: providing a die carrier; disposing at least one semiconductor die on the die carrier, the semiconductor die comprising at least one contact pad on a main face remote from the carrier; electrically connecting the semiconductor die or another electrical device with an electrical connector; applying an encapsulant above the semiconductor die, the die carrier, and the electrical connector; and screwing a metallic drilling screw through the encapsulant so that an end of the drilling screw contacts the electrical connector.

Abstract: A semiconductor device includes a die carrier, a semiconductor die disposed on a main face of the die carrier, the semiconductor die including one or more contact pads, an encapsulant covering at least partially the semiconductor die and at least a portion of the main face of the die carrier, an insulation layer covering the encapsulant, and one or more electrical interconnects, each being connected with one of the one or more contact pads of the semiconductor die and extending through the encapsulant.

Abstract: A device for controlling trapped ions includes a first semiconductor substrate. A second semiconductor substrate is disposed over the first semiconductor substrate. At least one ion trap is configured to trap ions in a space between the first semiconductor substrate and the second semiconductor substrate. A spacer is disposed between the first semiconductor substrate and the second semiconductor substrate, the spacer including an electrical interconnect which electrically connects a first metal layer structure of the first semiconductor substrate to a second metal layer structure of the second semiconductor substrate.

Abstract: A cold roll strip or sheet includes in (wt %) C 0.08-0.28; Mn 1.4-4.5; Cr 0.01-0.5; Si 0.01-2.5; Al 0.01-0.6; Si+Al?0.1; Si+Al+Cr?0.4; Nb?0.008; Ti?0.02; Mo?0.08; Ca?0.005; V?0.02; balance Fe apart from impurities. The steel is within the area defined by the coordinates A, B, C, D, where Ri/t (y-axle) is plotted vs TS(MPa)/YR (x-axle), and where A is [1200, 2), B is [2000, 4], C is [2000, 3], and D is [1200, 1].