Patents by Inventor Martin Gruber

Martin Gruber has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240132989
    Abstract: A cold roll strip or sheet includes in (wt %) C 0.08-0.28; Mn 1.4-4.5; Cr 0.01-0.5; Si 0.01-2.5; Al 0.01-0.6; Si+Al?0.1; Si+Al+Cr?0.4; Nb?0.008; Ti?0.02; Mo?0.08; Ca?0.005; V?0.02; balance Fe apart from impurities. The steel is within the area defined by the coordinates A, B, C, D, where Ri/t (y-axle) is plotted vs TS(MPa)/YR (x-axle), and where A is [1200, 2), B is [2000, 4], C is [2000, 3], and D is [1200, 1].
    Type: Application
    Filed: December 23, 2021
    Publication date: April 25, 2024
    Inventors: Michael SCHWARZENBRUNNER, Katharina STEINEDER, Martin GRUBER, Thomas MORTLBAUER
  • Publication number: 20240123757
    Abstract: A laminate with a decorative layer over an electrical functional layer such as a touch sensor panel, which provides for example a touchpad functionality, as well as a production method for it. It is possible for the first time to perform an individualization of prefabricated laminates with functionality such as touch functionality of a touch sensor in an uncomplicated manner. This is achieved by supplementing a functional laminate with a laser protective layer between the electrical functional layer and a decorative layer which can be lasered and written on with simple measures.
    Type: Application
    Filed: February 22, 2022
    Publication date: April 18, 2024
    Inventors: Wolfgang CLEMENS, Martin HAHN, Jörg STIERAND, Mathias GRUBER, Johannes SCHAD
  • Patent number: 11962320
    Abstract: A semiconductor chip providing on-chip self-testing of an Analog-to-Digital Converter, ADC, implemented in the semiconductor chip is provided. The semiconductor chip comprises the ADC and a Digital-to-Analog Converter, DAC, configured to generate and supply a radio frequency test signal to the ADC via a supply path. The ADC is configured to generate digital output data based on the radio frequency test signal. The semiconductor chip further comprises a reference data generation circuit configured to generate digital reference data. Additionally, the semiconductor chip comprises a comparator circuit configured to compare the digital output data to the digital reference in order to determine error data.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: April 16, 2024
    Assignee: Intel Corporation
    Inventors: Kameran Azadet, Martin Clara, Daniel Gruber, Albert Molina, Hundo Shin
  • Patent number: 11955407
    Abstract: An electronic module includes a semiconductor package including a die carrier, a semiconductor transistor die disposed on the die carrier, an electrical conductor connected to the semiconductor die, and an encapsulant covering the die carrier, the semiconductor die, and the electrical conductor so that a portion of the electrical conductor extends to the outside of the encapsulant. The electronic module further includes an interposer layer on which the semiconductor package is disposed, and a heat sink through which a cooling medium can flow. The interposer layer is disposed on the heatsink.
    Type: Grant
    Filed: January 18, 2021
    Date of Patent: April 9, 2024
    Assignee: Infineon Technologies Austria AG
    Inventors: Edward Fuergut, Davide Chiola, Martin Gruber, Wolfram Hable
  • Patent number: 11955415
    Abstract: The semiconductor device package comprises a die carrier, at least one semiconductor die disposed on the carrier, the semiconductor die comprising at least one contact pad on a main face remote from the carrier, an encapsulant disposed above the semiconductor die, an electrical connector electrically connected with the contact pad, a drilling screw screwed through the encapsulant and connected with the electrical connector.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: April 9, 2024
    Assignee: Infineon Technologies Austria AG
    Inventors: Thorsten Scharf, Thomas Bemmerl, Martin Gruber, Thorsten Meyer, Frank Singer
  • Publication number: 20240113026
    Abstract: A silicon carbide device includes a silicon carbide substrate, a contact layer located on the silicon carbide substrate and including nickel and silicon, a barrier layer structure including titanium and tungsten, and a metallization layer comprising copper, wherein the contact layer is located between the silicon carbide substrate and at least a part of the barrier layer structure, wherein the barrier layer structure is located between the silicon carbide substrate and the metallization layer, wherein the metallization layer is configured as a contact pad of the silicon carbide device.
    Type: Application
    Filed: December 1, 2023
    Publication date: April 4, 2024
    Inventors: Edward Fürgut, Ravi Keshav Joshi, Thomas Basler, Martin Gruber, Jochen Hilsenbeck, Wolfgang Scholz
  • Patent number: 11949446
    Abstract: The present disclosure relates to a concept for a transformer, a transmitter circuit, a semiconductor chip, a semiconductor package, a base station, a mobile device and a method for a radio frequency transmitter. The transformer for a radio frequency transmitter circuit comprises a primary coil and a secondary coils, which are configured to receive an input signal and to provide an output signal, and a ternary coil configured to provide a feedback signal.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: April 2, 2024
    Assignee: Intel Corporation
    Inventors: Daniel Gruber, Mark Elzinga, Martin Clara
  • Patent number: 11915999
    Abstract: A semiconductor device includes: a carrier including an electronic circuit; a plurality of semiconductor chip packages mounted on the carrier, each of the chip packages including an encapsulation encapsulating the semiconductor chip, a plurality of contact structures electrically connecting the semiconductor chip with the electronic circuit, and at least one cooling structure protruding from the encapsulation; and a cooling element thermally conductively connected to at least one cooling structure of each of at least two of the plurality of semiconductor chip packages.
    Type: Grant
    Filed: January 31, 2023
    Date of Patent: February 27, 2024
    Assignee: Infineon Technologies AG
    Inventors: Tomasz Naeve, Ralf Otremba, Thorsten Scharf, Markus Dinkel, Martin Gruber, Elvir Kahrimanovic
  • Patent number: 11862582
    Abstract: A package is disclosed. In one example, the package comprises a carrier, an electronic component mounted on the carrier, an encapsulant encapsulating at least part of the electronic component and at least part of the carrier and having a bottom side at a first vertical level. At least one lead is electrically coupled with the electronic component and comprising a first lead portion being encapsulated in the encapsulant and a second lead portion extending out of the encapsulant at the bottom side of the encapsulant. A functional structure at the bottom side extends up to a second vertical level different from the first vertical level.
    Type: Grant
    Filed: October 15, 2021
    Date of Patent: January 2, 2024
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Thomas Bemmerl, Martin Gruber, Martin Richard Niessner
  • Publication number: 20230402423
    Abstract: A semiconductor package is provided. The semiconductor package may include at least one semiconductor chip including a contact pad configured to conduct a current, a conductor element, wherein the conductor element is arranged laterally overlapping the contact pad and with a distance to the contact pad, at least one electrically conductive spacer, a first adhesive system configured to electrically and mechanically connect the at least one electrically conductive spacer with the contact pad, and a second adhesive system configured to electrically and mechanically connect the at least one electrically conductive spacer with the conductor element, wherein the conductor element is electrically conductively connected to a clip or is at least part of a clip, and wherein the spacer is configured to electrically conductively connect the contact pad with the laterally overlapping portion of the conductor element.
    Type: Application
    Filed: June 16, 2023
    Publication date: December 14, 2023
    Inventors: Edward Fuergut, Ralf Otremba, Irmgard Escher-Poeppel, Martin Gruber
  • Publication number: 20230282608
    Abstract: A semiconductor die package includes a semiconductor transistor die having a contact pad on an upper main face. The semiconductor die package also includes an electrical conductor disposed on the contact pad and fabricated by laser-assisted structuring of a metallic material, and an encapsulant covering the semiconductor die and at least a portion of the electrical conductor.
    Type: Application
    Filed: April 10, 2023
    Publication date: September 7, 2023
    Inventors: Edward Fürgut, Irmgard Escher-Poeppel, Martin Gruber, Ivan Nikitin, Hans-Joachim Schulze
  • Patent number: 11728250
    Abstract: A semiconductor package includes a first die pad, a first semiconductor die mounted on the first die pad, an encapsulant body of electrically insulating material that encapsulates first die pad and the first semiconductor die, a plurality of package leads that each protrude out of a first outer face of the encapsulant body, a connection lug that protrudes out of a second outer face of the encapsulant body, the second outer face being opposite from the first outer face. The first semiconductor die includes first and second voltage blocking terminals. The connection lug is electrically connected to one of the first and second voltage blocking terminals of the first semiconductor die. A first one of the package leads is electrically connected to an opposite one of the first and second voltage blocking terminals of the first semiconductor die that the first connection lug is electrically connected to.
    Type: Grant
    Filed: May 20, 2021
    Date of Patent: August 15, 2023
    Assignee: Infineon Technologies Austria AG
    Inventors: Edward Fuergut, Martin Gruber, Herbert Hopfgartner, Bernd Schmoelzer
  • Patent number: 11721616
    Abstract: A semiconductor package includes a die pad comprising a die attach surface, a first lead extending away from the die pad, one or more semiconductor dies mounted on the die attach surface, the one or more semiconductor dies comprising first and second bond pads that each face away from the die attach surface, and a distribution element that provides a first transmission path for a first electrical signal between the first lead and the first bond pad of the one or more semiconductor dies and a second transmission path for the first electrical signal between the first lead and the second bond pad of the one or more semiconductor dies. The distribution element comprises at least one integrally formed circuit element that creates a difference in transmission characteristics between the first and second transmission paths.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: August 8, 2023
    Assignee: Infineon Technologies Austria AG
    Inventors: Stephan Voss, Edward Fuergut, Martin Gruber, Andreas Huerner, Anton Mauder
  • Patent number: 11715719
    Abstract: A semiconductor package is provided. The semiconductor package may include at least one semiconductor chip including a contact pad configured to conduct a current, a conductor element, wherein the conductor element is arranged laterally overlapping the contact pad and with a distance to the contact pad, at least one electrically conductive spacer, a first adhesive system configured to electrically and mechanically connect the at least one electrically conductive spacer with the contact pad, and a second adhesive system configured to electrically and mechanically connect the at least one electrically conductive spacer with the conductor element, wherein the conductor element is electrically conductively connected to a clip or is at least part of a clip, and wherein the spacer is configured to electrically conductively connect the contact pad with the laterally overlapping portion of the conductor element.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: August 1, 2023
    Assignee: Infineon Technologies AG
    Inventors: Edward Fuergut, Ralf Otremba, Irmgard Escher-Poeppel, Martin Gruber
  • Patent number: 11710684
    Abstract: A package is disclosed. In one example, the package comprises a substrate having at least one first recess on a front side and at least one second recess on a back side, wherein the substrate is separated into a plurality of separate substrate sections by the at least one first recess and the at least one second recess, an electronic component mounted on the front side of the substrate, and a single encapsulant filling at least part of the at least one first recess and at least part of the at least one second recess. The encapsulant fully circumferentially surrounds sidewalls of at least one of the substrate sections.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: July 25, 2023
    Assignee: Infineon Technologies AG
    Inventors: Frank Singer, Martin Gruber, Thorsten Meyer, Thorsten Scharf, Peter Strobel, Stefan Woetzel
  • Patent number: 11688713
    Abstract: A method for fabricating a semiconductor die package includes: providing a semiconductor transistor die, the semiconductor transistor die having a first contact pad on a first lower main face and/or a second contact pad on an upper main face; fabricating a frontside electrical conductor onto the second contact pad and a backside electrical conductor onto the first contact pad; and applying an encapsulant covering the semiconductor die and at least a portion of the electrical conductor, wherein the frontside electrical conductor and/or the backside electrical conductor is fabricated by laser-assisted structuring of a metallic structure.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: June 27, 2023
    Assignee: Infineon Technologies Austria AG
    Inventors: Edward Fuergut, Irmgard Escher-Poeppel, Martin Gruber, Ivan Nikitin, Hans-Joachim Schulze
  • Publication number: 20230187326
    Abstract: A semiconductor device includes: a carrier including an electronic circuit; a plurality of semiconductor chip packages mounted on the carrier, each of the chip packages including an encapsulation encapsulating the semiconductor chip, a plurality of contact structures electrically connecting the semiconductor chip with the electronic circuit, and at least one cooling structure protruding from the encapsulation; and a cooling element thermally conductively connected to at least one cooling structure of each of at least two of the plurality of semiconductor chip packages.
    Type: Application
    Filed: January 31, 2023
    Publication date: June 15, 2023
    Inventors: Tomasz Naeve, Ralf Otremba, Thorsten Scharf, Markus Dinkel, Martin Gruber, Elvir Kahrimanovic
  • Publication number: 20230178428
    Abstract: A method includes providing a lead frame with a central metal plate and a plurality of leads extending away from the central metal plate, the central metal plate including an upper surface that includes a first mesa that is elevated from recessed regions, mounting a semiconductor die on the upper surface of central metal plate such that a lower surface of the semiconductor die is at least partially disposed on the first mesa, forming electrical interconnections between terminals of the semiconductor die and the leads, forming an encapsulant body on the central metal plate such that the semiconductor die is encapsulated by the encapsulant body and such that the leads protrude out from edge sides of the encapsulant body, and thinning the central metal plate from a rear surface of the central metal plate so as to isolate the first mesa at a lower surface of the encapsulant body.
    Type: Application
    Filed: December 6, 2021
    Publication date: June 8, 2023
    Inventors: Thorsten Meyer, Fee Hoon Wendy Wong, Thomas Behrens, Eric Lopez Bonifacio, Chau Fatt Chiang, Irmgard Escher-Poeppel, Giovanni Ragasa Garbin, Martin Gruber, Tien Shyang Law, Mohamad Azian Mohamed Azizi, Si Hao Vincent Yeo
  • Patent number: 11600558
    Abstract: A chip package is provided. The chip package includes a semiconductor chip having on a front side a first connecting pad and a second connecting pad, a carrier having a pad contact area and a recess, encapsulation material encapsulating the conductor chip, a first external connection that is free from or extends out of the encapsulation material, an electrically conductive clip, and a contact structure. The semiconductor chip is arranged with its front side facing the carrier with the first connecting pad over the recess and with the second connecting pad contacting the pad contact area. The clip is arranged over a back side of the semiconductor chip covering the semiconductor chip where it extends over the recess. The electrically conductive contact structure electrically conductively connects the first connecting pad with the first external connection.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: March 7, 2023
    Assignee: Infineon Technologies AG
    Inventors: Tomasz Naeve, Ralf Otremba, Thorsten Scharf, Markus Dinkel, Martin Gruber, Elvir Kahrimanovic
  • Publication number: 20230051100
    Abstract: A molded semiconductor package includes a lead frame having one or more first leads monolithically formed with a die pad and extending outward from the pad in a first direction. A semiconductor die is attached to the die pad at a first side of the die. A metal clip of a clip frame is attached to a power terminal at a second side of the die. One or more second leads monolithically formed with the metal clip extend outward from the clip in a second direction different than the first direction. A mold compound embeds the die. The first lead(s) and the second lead(s) are exposed at different sides of the mold compound and do not vertically overlap with one another. Within the mold compound, the clip transitions from a first level above the power terminal to a second level in a same plane as the leads.
    Type: Application
    Filed: November 3, 2022
    Publication date: February 16, 2023
    Inventors: Bun Kian Tay, Mei Yih Goh, Martin Gruber, Josef Hoeglauer, Michael Juerss, Josef Maerz, Thorsten Meyer, Thorsten Scharf, Chee Voon Tan