Patents by Inventor Martin Gruber

Martin Gruber has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10037972
    Abstract: Various embodiments provide an electronic module comprising a interposer comprising a fluid channel formed in an electrically isolating material and an electrically conductive structured layer; at least one electronic chip attached to the electrically conductive layer and in thermal contact to the fluid channel; and a molded encapsulation formed at least partially around the at least one electronic chip, wherein the electrically conductive structured layer is directly formed on the electrically isolating material.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: July 31, 2018
    Assignee: Infineon Technologies AG
    Inventors: Edward Fuergut, Martin Gruber, Wolfram Hable
  • Patent number: 10014275
    Abstract: One aspect of the invention relates to a method for producing a chip assemblage. Two or more chip assemblies are produced in each case by cohesively and electrically conductively connecting an electrically conductive first compensation lamina to a first main electrode of a semiconductor chip. A control electrode interconnection structure is arranged in a free space between the chip assemblies. Electrically conductive connections are produced between the control electrode interconnection structure and control electrodes of the semiconductor chips of the individual chip assemblies. The chip assemblies are cohesively connected by means of a dielectric embedding compound.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: July 3, 2018
    Assignee: Infineon Technologies AG
    Inventors: Alexander Heinrich, Irmgard Escher-Poeppel, Martin Gruber, Andreas Munding, Catharina Wille
  • Publication number: 20180166366
    Abstract: A semiconductor device includes a first lead frame, a second lead frame, a first semiconductor chip, and an encapsulation material. The first lead frame includes a first die pad having a first surface and a second surface opposite to the first surface. The second lead frame includes a second die pad having a first surface and a second surface opposite to the first surface. The first surface of the second die pad faces the first surface of the first die pad. The first semiconductor chip is attached to the first surface of the first die pad. The encapsulation material encapsulates the first semiconductor chip and portions of the first lead frame and the second lead frame. The encapsulation material has a first surface aligned with the second surface of the first die pad and a second surface aligned with the second surface of the second die pad.
    Type: Application
    Filed: December 12, 2016
    Publication date: June 14, 2018
    Applicant: Infineon Technologies Austria AG
    Inventors: Edward Fuergut, Martin Gruber, Wolfgang Scholz, Ralf Otremba
  • Publication number: 20180050296
    Abstract: A filter element with at least one filter medium body and with a grip configured to hold and guide the filter element is provided. At least one locking element is arranged at the grip and configured to lock the filter element on a receiving filter housing. A filter device with such a filter element has a receiving filter housing to receive the filter element and a cover to secure the locking element in locked position on the filter housing.
    Type: Application
    Filed: October 13, 2017
    Publication date: February 22, 2018
    Inventors: Torsten Fritzsching, Pedro Miguel Pereira Madeira, Andreas Franz, Nadine Donauer, Martin Gruber, Joachim-Paul Krieger, Marcel Holzwarth, Manfred Winter
  • Patent number: 9857439
    Abstract: A sensor arrangement is provided. The sensor arrangement may include at least one sensor element having a first side and a second side opposite the first side and configured for sensing a magnetic field; and an electrically conductive line, wherein a first portion of the electrically conductive line may be arranged on the first side of the at least one sensor element and a second portion of the electrically conductive line may be arranged on the second side of the at least one sensor element in such a way that if a current is flowing through the electrically conductive line, the current has a first direction in the first portion and a second direction opposite the first direction in the second portion, such that a first magnetic field formed by the current in the first portion and a second magnetic field formed by the current in the second portion may at least partly add constructively at a sensing portion of the at least one sensor element.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: January 2, 2018
    Assignee: Infineon Technologies AG
    Inventors: Franz Jost, Holger Wille, Martin Gruber
  • Publication number: 20170271298
    Abstract: One aspect of the invention relates to a method for producing a chip assemblage. Two or more chip assemblies are produced in each case by cohesively and electrically conductively connecting an electrically conductive first compensation lamina to a first main electrode of a semiconductor chip. A control electrode interconnection structure is arranged in a free space between the chip assemblies. Electrically conductive connections are produced between the control electrode interconnection structure and control electrodes of the semiconductor chips of the individual chip assemblies. The chip assemblies are cohesively connected by means of a dielectric embedding compound.
    Type: Application
    Filed: March 15, 2017
    Publication date: September 21, 2017
    Applicant: Infineon Technologies AG
    Inventors: Alexander Heinrich, Irmgard Escher-Poeppel, Martin Gruber, Andreas Munding, Catharina Wille
  • Publication number: 20170229399
    Abstract: The method comprises providing a plurality of electronic devices, embedding the electronic devices in an encapsulation layer, forming vias into the encapsulation layer, the vias extending from a main face of the encapsulation layer to the electronic devices, and depositing a metallic layer onto the encapsulation layer including the vias by galvanic plating, the method further comprising providing a current distribution layer for effecting a distributed growth of the metallic material during the galvanic plating.
    Type: Application
    Filed: February 7, 2017
    Publication date: August 10, 2017
    Inventors: Martin Gruber, Steffen Jordan
  • Publication number: 20170200666
    Abstract: A semiconductor chip package is disclosed. The package includes a carrier, a plurality of semiconductor chips disposed on the carrier, a first encapsulation layer disposed above the semiconductor chips. A metallization layer is disposed above the first encapsulation layer, the metallization layer including a plurality of first metallic areas forming electrical connections between selected ones of the semiconductor chips. A second encapsulation layer is disposed above the solder resist layer. A plurality of external connectors are provided, each one of the external connectors being connected with one of the first metallic areas and extending outwardly through a surface of the second encapsulation layer.
    Type: Application
    Filed: October 13, 2016
    Publication date: July 13, 2017
    Applicant: Infineon Technologies AG
    Inventors: Wolfram Hable, Martin Gruber, Juergen Hoegerl
  • Publication number: 20170125395
    Abstract: In order to produce a power semiconductor module, a circuit carrier is populated with a semiconductor chip and with an electrically conductive contact element. After populating, the semiconductor chip and the contact element are embedded into a dielectric embedding compound, and the contact element is exposed. In addition, an electrically conductive base layer is produced which electrically contacts the exposed contact element and which bears on the embedding compound and the exposed contact element. A prefabricated metal film is applied to the base layer by means of an electrically conductive connection layer.
    Type: Application
    Filed: October 28, 2016
    Publication date: May 4, 2017
    Inventors: Olaf Hohlfeld, Guido Boenig, Irmgard Escher-Poeppel, Edward Fuergut, Martin Gruber, Thorsten Meyer
  • Publication number: 20170051452
    Abstract: The invention relates to a method for brightening dyed textiles and to the textiles thereby produced. The method is characterized by treating the materials with an aqueous liquor containing an organic peroxocarboxylic acid having a hydrophobic group, consisting of at least 5 C atoms, as the active component.
    Type: Application
    Filed: April 15, 2015
    Publication date: February 23, 2017
    Applicant: CHT R. BEITLICH GMBH
    Inventors: Martin GRUBER, Thomas APLAS, Harald LUTZ
  • Patent number: 9564578
    Abstract: A semiconductor package includes a semiconductor die attached to a substrate and a magnetic field sensor included as part of the same semiconductor package as the semiconductor die and positioned in close proximity to a current pathway of the semiconductor die so that the magnetic field sensor can sense a magnetic field produced by current flowing in the current pathway. The magnetic field sensor includes a first magnetic field sensing component galvanically isolated from the current pathway and positioned so that a magnetic field produced by current flowing in the current pathway impinges on the first magnetic field sensing component in a first direction. The magnetic field sensor also includes a second magnetic field sensing component galvanically isolated from the current pathway and positioned so that the magnetic field impinges on the second magnetic field sensing component in a second direction different than the first direction.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: February 7, 2017
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Martin Gruber, Rainer Markus Schaller, Franz Jost, Stefan Mieslinger, Liu Chen, Toni Salminen, Giuliano Angelo Babulano, Jens Oetjen, Markus Dinkel
  • Publication number: 20160380181
    Abstract: A semiconductor package includes a semiconductor die attached to a substrate and a magnetic field sensor included as part of the same semiconductor package as the semiconductor die and positioned in close proximity to a current pathway of the semiconductor die so that the magnetic field sensor can sense a magnetic field produced by current flowing in the current pathway. The magnetic field sensor includes a first magnetic field sensing component galvanically isolated from the current pathway and positioned so that a magnetic field produced by current flowing in the current pathway impinges on the first magnetic field sensing component in a first direction. The magnetic field sensor also includes a second magnetic field sensing component galvanically isolated from the current pathway and positioned so that the magnetic field impinges on the second magnetic field sensing component in a second direction different than the first direction.
    Type: Application
    Filed: November 20, 2015
    Publication date: December 29, 2016
    Inventors: Thorsten Meyer, Martin Gruber, Rainer Markus Schaller, Franz Jost, Stefan Mieslinger, Liu Chen, Toni Salminen, Giuliano Angelo Babulano, Jens Oetjen, Markus Dinkel
  • Publication number: 20160377689
    Abstract: An interconnect module includes a metal clip having a first end section, a second end section and a middle section extending between the first and the second end sections. The first end section is configured for external attachment to a bare semiconductor die or packaged semiconductor die attached to a carrier or to a metal region of the carrier. The second end section is configured for external attachment to a different metal region of the carrier or to a different semiconductor die or packaged semiconductor die attached to the carrier. The module further includes a magnetic field sensor secured to the metal clip. The magnetic field sensor is operable to sense a magnetic field produced by current flowing through the metal clip. The interconnect module can be used to form a direct electrical connection between components and/or metal regions of a carrier to which the module is attached.
    Type: Application
    Filed: February 22, 2016
    Publication date: December 29, 2016
    Inventors: Giuliano Angelo Babulano, Jens Oetjen, Liu Chen, Toni Salminen, Stefan Mieslinger, Markus Dinkel, Martin Gruber, Franz Jost, Thorsten Meyer, Rainer Schaller
  • Patent number: 9524932
    Abstract: Semiconductor chips are described that combine a semiconductor device and a capacitor onto a single substrate such that the semiconductor device and the capacitor are electrically isolated from each other. In one example, a semiconductor chip includes a substrate having a first side and a second side, wherein the second side is opposite the first side. The semiconductor chip further includes a semiconductor device formed on the first side of the substrate and an electrically insulating layer formed on at least a portion of the second side of the substrate. The semiconductor chip further includes a capacitor device formed on at least a portion of the electrically insulating layer on the second side of the substrate, wherein the capacitor device is electrically insulated from the semiconductor device.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: December 20, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Andreas Munding, Martin Gruber
  • Publication number: 20160322333
    Abstract: Various embodiments provide an electronic module comprising a interposer comprising a fluid channel formed in an electrically isolating material and an electrically conductive structured layer; at least one electronic chip attached to the electrically conductive layer and in thermal contact to the fluid channel; and a molded encapsulation formed at least partially around the at least one electronic chip, wherein the electrically conductive structured layer is directly formed on the electrically isolating material.
    Type: Application
    Filed: April 25, 2016
    Publication date: November 3, 2016
    Inventors: Edward FUERGUT, Martin GRUBER, Wolfram HABLE
  • Publication number: 20160316567
    Abstract: A semiconductor module includes a circuit board and a power semiconductor chip embedded in the circuit board. The power semiconductor chip has a first load electrode. The semiconductor module further includes a power terminal connector electrically connected to the first load electrode. The embedded power semiconductor chip is positioned laterally within a footprint zone of the power terminal connector.
    Type: Application
    Filed: April 21, 2016
    Publication date: October 27, 2016
    Inventors: Martin Gruber, Angela Kessler, Thorsten Scharf
  • Publication number: 20160216342
    Abstract: A sensor arrangement is provided. The sensor arrangement may include at least one sensor element having a first side and a second side opposite the first side and configured for sensing a magnetic field; and an electrically conductive line, wherein a first portion of the electrically conductive line may be arranged on the first side of the at least one sensor element and a second portion of the electrically conductive line may be arranged on the second side of the at least one sensor element in such a way that if a current is flowing through the electrically conductive line, the current has a first direction in the first portion and a second direction opposite the first direction in the second portion, such that a first magnetic field formed by the current in the first portion and a second magnetic field formed by the current in the second portion may at least partly add constructively at a sensing portion of the at least one sensor element.
    Type: Application
    Filed: January 13, 2016
    Publication date: July 28, 2016
    Inventors: Franz JOST, Holger WILLE, Martin GRUBER
  • Publication number: 20160099207
    Abstract: An electronic module includes a first insulation layer, at least one carrier having a first main surface, a second main surface situated opposite the first main surface, and side surfaces connecting the first and second main surfaces to one another, at least one semiconductor chip arranged on the second main surface of the carrier, wherein the semiconductor chip has contact elements, and a second insulation layer, which is arranged on the carrier and the semiconductor chip.
    Type: Application
    Filed: October 6, 2015
    Publication date: April 7, 2016
    Inventors: Edward Fuergut, Martin Gruber, Juergen Hoegerl
  • Publication number: 20150311149
    Abstract: Semiconductor chips are described that combine a semiconductor device and a capacitor onto a single substrate such that the semiconductor device and the capacitor are electrically isolated from each other. In one example, a semiconductor chip includes a substrate having a first side and a second side, wherein the second side is opposite the first side. The semiconductor chip further includes a semiconductor device formed on the first side of the substrate and an electrically insulating layer formed on at least a portion of the second side of the substrate. The semiconductor chip further includes a capacitor device formed on at least a portion of the electrically insulating layer on the second side of the substrate, wherein the capacitor device is electrically insulated from the semiconductor device.
    Type: Application
    Filed: July 2, 2015
    Publication date: October 29, 2015
    Inventors: Andreas Munding, Martin Gruber
  • Patent number: 9140735
    Abstract: A method of manufacturing an electronic circuit with an integrally formed capability of providing information indicative of a value of a current flowing in the electronic circuit, wherein the method comprises forming an electrically conductive wiring structure on a substrate, configuring a first section of the wiring structure for contributing to a predefined use function of the electronic circuit, and configuring a second section of the wiring structure for providing information indicative of the value of the current flowing in the electronic circuit upon applying a stimulus signal to the second section, wherein at least a part of the configuring of the first section and the configuring of the second section is performed simultaneously.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: September 22, 2015
    Assignee: Infineon Technologies AG
    Inventors: Martin Gruber, Angela Kessler