Abstract: The Schottky barrier diode comprises a semiconductor body with a main surface, a doped region and a further doped region of the semiconductor body, which extend to the main surface, the doped region and the further doped region having opposite types of electric conductivity, a subregion and a further subregion of the further doped region, the subregions being contiguous with one another, the further subregion comprising a higher doping concentration than the subregion, a silicide layer on the main surface, the silicide layer forming an interface with the doped region, an electric contact on the doped region, and a further electric contact electrically connecting the further doped region with the silicide layer.

Abstract: The Schottky barrier diode comprises a semiconductor body with a main surface, a doped region and a further doped region of the semiconductor body, which extend to the main surface, the doped region and the further doped region having opposite types of electric conductivity, a subregion and a further subregion of the further doped region, the subregions being contiguous with one another, the further subregion comprising a higher doping concentration than the subregion, a silicide layer on the main surface, the silicide layer forming an interface with the doped region, an electric contact on the doped region, and a further electric contact electrically connecting the further doped region with the silicide layer.

Abstract: The field effect transistor device comprises a substrate (1) of semiconductor material, a body well of a first type of electric conductivity in the substrate, a source region in the body well, the source region having an opposite second type of electric conductivity, a source contact (3) on the source region, a body contact region of the first type of electric conductivity in the body well, a body contact (5) on the body contact region, and a gate electrode layer (2) partially overlapping the body well. A portion (2*) of the gate electrode layer (2) is present between the source contact (3) and the body contact (5).

Abstract: The field effect transistor device comprises a substrate (1) of semiconductor material, a body well of a first type of electric conductivity in the substrate, a source region in the body well, the source region having an opposite second type of electric conductivity, a source contact (3) on the source region, a body contact region of the first type of electric conductivity in the body well, a body contact (5) on the body contact region, and a gate electrode layer (2) partially overlapping the body well. A portion (2*) of the gate electrode layer (2) is present between the source contact (3) and the body contact (5).

Abstract: The method comprises implanting a deep well of a first type of electrical conductivity provided for a drift region in a substrate of semiconductor material, the deep well of the first type comprising a periphery, implanting a deep well or a plurality of deep wells of a second type of electrical conductivity opposite to the first type of electrical conductivity at the periphery of the deep well of the first type, implanting shallow wells of the first type of electrical conductivity at the periphery of the deep well of the first type, the shallow wells of the first type extending into the deep well of the first type; and implanting shallow wells of the second type of electrical conductivity adjacent to the deep well of the first type between the shallow wells of the first type of electrical conductivity.

Abstract: The method comprises implanting a deep well of a first type of electrical conductivity provided for a drift region in a substrate of semiconductor material, the deep well of the first type comprising a periphery, implanting a deep well or a plurality of deep wells of a second type of electrical conductivity opposite to the first type of electrical conductivity at the periphery of the deep well of the first type, implanting shallow wells of the first type of electrical conductivity at the periphery of the deep well of the first type, the shallow wells of the first type extending into the deep well of the first type; and implanting shallow wells of the second type of electrical conductivity adjacent to the deep well of the first type between the shallow wells of the first type of electrical conductivity.

Abstract: The semiconductor drift device comprises a deep well of a first type of electrical conductivity provided for a drift region in a substrate of semiconductor material, a drain region of the first type of conductivity at the surface of the substrate, a plurality of source regions of the first type of conductivity in shallow wells of the first type of conductivity at the periphery of the deep well of the first type, and a deep well or a plurality of deep wells of an opposite second type of electrical conductivity provided for a plurality of gate regions at the periphery of the deep well of the first type. The gate regions are formed by shallow wells of the second type of electrical conductivity, which are arranged in the deep well of the second type between the shallow wells of the first type.

Abstract: The high-voltage transistor device comprises a semiconductor substrate (1) with a source region (2) of a first type of electrical conductivity, a body region (3) including a channel region (4) of a second type of electrical conductivity opposite to the first type of conductivity, a drift region (5) of the first type of conductivity, and a drain region (6) of the first type of conductivity extending longitudinally in striplike fashion from the channel region (4) to the drain region (6) and laterally confined by isolation regions (9). The drift region (5) comprises a doping of the first type of conductivity and includes an additional region (8) with a net doping of the second type of conductivity to adjust the electrical properties of the drift region (5). The drift region depth and the additional region depth do not exceed the maximal depth (17) of the isolation regions (9).

Abstract: The high-voltage transistor device has a p-type semiconductor substrate that is furnished with a p-type epitaxial layer. A well and a body region are located in the epitaxial layer. A source region is arranged in the body region, and a drain region is arranged in the well. A channel region is located in the body region between the well and the source region. A gate electrode is arranged above the channel region. In the part of the semiconductor substrate and the epitaxial layer underneath the source region and the channel region, a deep body region is present, which has a higher dopant concentration in comparison to the remainder of the semiconductor substrate.

Abstract: The semiconductor drift device comprises a deep well of a first type of electrical conductivity (1) provided for a drift region in a substrate of semiconductor material, a drain region (6) of the first type of conductivity at the surface of the substrate, a plurality of source regions (5) of the first type of conductivity in shallow wells of the first type of conductivity (3) at the periphery of the deep well of the first type (1), and a deep well or a plurality of deep wells of an opposite second type of electrical conductivity (2) provided for a plurality of gate regions at the periphery of the deep well of the first type (1). The gate regions are formed by shallow wells of the second type of electrical conductivity (4), which are arranged in the deep well of the second type (2) between the shallow wells of the first type (3).

Abstract: The high-voltage transistor device comprises a semiconductor substrate (1) with a source region (2) of a first type of electrical conductivity, a body region (3) including a channel region (4) of a second type of electrical conductivity opposite to the first type of conductivity, a drift region (5) of the first type of conductivity, and a drain region (6) of the first type of conductivity extending longitudinally in striplike fashion from the channel region (4) to the drain region (6) and laterally confined by isolation regions (9). The drift region (5) comprises a doping of the first type of conductivity and includes an additional region (8) with a net doping of the second type of conductivity to adjust the electrical properties of the drift region (5). The drift region depth and the additional region depth do not exceed the maximal depth (17) of the isolation regions (9).

Abstract: The high-voltage transistor device comprises a semiconductor substrate (1) with a source region (2) of a first type of electrical conductivity, a body region (3) including a channel region (4) of a second type of electrical conductivity opposite to the first type of conductivity, a drift region (5) of the first type of conductivity, and a drain region (6) of the first type of conductivity extending longitudinally in striplike fashion from the channel region (4) to the drain region (6) and laterally confined by isolation regions (9). The drift region (5) comprises a doping of the first type of conductivity and includes an additional region (8) with a net doping of the second type of conductivity to adjust the electrical properties of the drift region (5). The drift region depth and the additional region depth do not exceed the maximal depth (17) of the isolation regions (9).

Abstract: A high-voltage NMOS transistor with low threshold voltage. The body doping that defines the channel region is in the form of a deep p-well. An additional shallow p-doping is arranged as a channel stopper on the transistor head. This additional shallow p-doping is produced in the semiconductor substrate at the end of the deep p-well that faces away from the channel region, and extends up to a location underneath a field oxide region that encloses the active window. The leakage current of the parasitic transistor at the transistor head is suppressed with the channel stopper.

Abstract: A high voltage JFET has a deep well of a first type of conductivity made in a semiconductor substrate, a further well of an opposite second type of conductivity arranged in the deep well, a shallow well of a first type of conductivity arranged in the further well, a first contact region for source and a second contact region for drain arranged in the further well, a third contact region for gate arranged between the first contact region and the second contact region in the shallow well, a first distance between the first contact region and the third contact region being smaller than a second distance between the second contact region and the third contact region, and an electrical connection between the first contact region and the second contact region via at least one channel region present between the deep well and the shallow well in the further well.

Abstract: A body region (3) with a first type of electric conductivity is arranged at the upper surface (10) of a substrate (1) in a well (2), wherein a portion of the well that is not occupied by the body region has a second type of conductivity opposite the first type of conductivity. At the upper surface, a source region is arranged in the body region and a drain region is arranged in the well at a distance from the body region; the source region and the drain region both have the second type of conductivity. The body region is arranged underneath a surface area of the upper surface that has a border (7) with opposing first border sides (8). The well has a varying depth in the substrate. The depth of the well is smaller underneath the first border sides of the body region than in a portion of the body region that is spaced apart from the first border sides.

Abstract: The high-voltage transistor device comprises a semiconductor substrate (1) with a source region (2) of a first type of electrical conductivity, a body region (3) including a channel region (4) of a second type of electrical conductivity opposite to the first type of conductivity, a drift region (5) of the first type of conductivity, and a drain region (6) of the first type of conductivity extending longitudinally in striplike fashion from the channel region (4) to the drain region (6) and laterally confined by isolation regions (9). The drift region (5) comprises a doping of the first type of conductivity and includes an additional region (8) with a net doping of the second type of conductivity to adjust the electrical properties of the drift region (5). The drift region depth and the additional region depth do not exceed the maximal depth (17) of the isolation regions (9).

Abstract: The p-channel LDMOS transistor comprises a semiconductor substrate (1), an n well (2) of n-type conductivity in the substrate, and a p well (3) of p-type conductivity in the n well. A portion of the n well is located under the p well. A drain region (4) of p-type conductivity is arranged in the p well, and a source region (9) of p-type conductivity is arranged in the n well. A gate dielectric (7) is arranged on the substrate, and a gate electrode (8) is arranged on the gate dielectric. A body contact region (14) of n-type conductivity is arranged in the n well. A p implant region (17) is arranged in the n well under the p well in the vicinity of the p well. The p implant region locally compensates n-type dopants of the n well.

Abstract: The high-voltage transistor device has a p-type semiconductor substrate (1) that is furnished with a p-type epitaxial layer (2). A well (3) and a body region (4) are located in the epitaxial layer. A source region (5) is arranged in the body region, and a drain region (6) is arranged in the well. A channel region (7) is located in the body region between the well and the source region. A gate electrode (8) is arranged above the channel region. In the part of the semiconductor substrate and the epitaxial layer underneath the source region and the channel region, a deep body region (11) is present, which has a higher dopant concentration in comparison to the remainder of the semiconductor substrate.

Abstract: A body region (3) with a first type of electric conductivity is arranged at the upper surface (10) of a substrate (1) in a well (2), wherein a portion of the well that is not occupied by the body region has a second type of conductivity opposite the first type of conductivity. At the upper surface, a source region is arranged in the body region and a drain region is arranged in the well at a distance from the body region; the source region and the drain region both have the second type of conductivity. The body region is arranged underneath a surface area of the upper surface that has a border (7) with opposing first border sides (8). The well has a varying depth in the substrate. The depth of the well is smaller underneath the first border sides of the body region than in a portion of the body region that is spaced apart from the first border sides.

Abstract: The p-channel LDMOS transistor comprises a semiconductor substrate (1), an n well (2) of n-type conductivity in the substrate, and a p well (3) of p-type conductivity in the n well. A portion of the n well is located under the p well. A drain region (4) of p-type conductivity is arranged in the p well, and a source region (9) of p-type conductivity is arranged in the n well. A gate dielectric (7) is arranged on the substrate, and a gate electrode (8) is arranged on the gate dielectric. A body contact region (14) of n-type conductivity is arranged in the n well. A p implant region (17) is arranged in the n well under the p well in the vicinity of the p well. The p implant region locally compensates n-type dopants of the n well.