Abstract: In a high-voltage PMOS transistor having an insulated gate electrode (18), a p-conductive source (15) in an n-conductive well (11), a p-conductive drain (14) in a p-conductive well (12) which is arranged in the n-conductive well, and having a field oxide area (13) between the gate electrode and drain, the depth (A?-B?) of the n-conductive well underneath the drain (14) is less than underneath the source (15), and the depth (A?-B?) of the p-conductive well is greatest underneath the drain (14).

Abstract: An n-conductively doped source region (2) in a deep p-conducting well (DP), a channel region (13), a drift region (14) formed by a counterdoping region (12), preferably below a gate field plate (6) insulated by a gate field oxide (8), and an n-conductively doped drain region (3) arranged in a deep n-conducting well (DN) are arranged in this order at a top side of a substrate (1). A lateral junction (11) between the deep p-conducting well (DP) and the deep n-conducting well (DN) is present in the drift path (14) in the vicinity of the drain region (3) so as to avoid a high voltage drop in the channel region (13) during the operation of the transistor and to achieve a high threshold voltage and also a high breakdown voltage between source and drain.