Patents by Inventor Martin Liu
Martin Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180363844Abstract: Disclosed is a rotary suction cup, comprising a knob, a base, and a rubber bottom arranged from top to bottom, wherein the knob is connected with the rubber bottom, and the base is provided with a connecting portion for connecting a hanging object, and a through hole; the rotary suction cup further comprising: a pivot seat, arranged in the middle of the rubber bottom, and connected with the knob; a pivot tube, arranged in the knob, and sleeved on and moveably connected to the pivot seat; wherein, the pivot seat is axially moved along with the rotation of the pivot tube, the rubber bottom is concavely deformed on a surface thereof by the pivot seat, and the pivot tube or the knob is rotationally connected to the base in a stepped manner of at least two steps.Type: ApplicationFiled: March 6, 2018Publication date: December 20, 2018Applicant: Guangzhou Homfel Ltd.Inventor: Martin Liu
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Patent number: 9337168Abstract: Provided is a wafer level packaging. The packaging includes a first semiconductor wafer having a transistor device and a first bonding layer that includes a first material. The packaging includes a second semiconductor wafer having a second bonding layer that includes a second material different from the first material, one of the first and second materials being aluminum-based, and the other thereof being titanium-based. Wherein a portion of the second wafer is diffusively bonded to the first wafer through the first and second bonding layers.Type: GrantFiled: February 6, 2014Date of Patent: May 10, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Richard Chu, Martin Liu, Chia-Hua Chu, Yuan-Chih Hsieh, Chung-Hsien Lin, Lan-Lin Chao, Chun-Wen Cheng, Mingo Liu
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Patent number: 8964413Abstract: A resonant converter comprising: a controllable current source; a resonant tank circuit coupled to the current source; and an isolated buck-type converter coupled to the resonant tank circuit, the isolated buck-type converter having an output, wherein the resonant tank circuit enables switches in the isolated buck-type converter to switch under soft-switching conditions. In some embodiments, the controllable current source is a switch-mode-type current source. In some embodiments, the isolated buck-type converter comprises a half-bridge converter. In some embodiments, the isolated buck-type converter comprises a full-bridge converter. In some embodiments, the isolated buck-type converter comprises a push-pull converter.Type: GrantFiled: April 22, 2010Date of Patent: February 24, 2015Assignee: Flextronics AP, LLCInventor: Martin Liu
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Patent number: 8851133Abstract: Provided is an apparatus and a method of holding a device. The apparatus includes a wafer chuck having first and second holes that extend therethrough, and a pressure control structure that can independently and selectively vary a fluid pressure in each of the first and second holes between pressures above and below an ambient pressure. The method includes providing a wafer chuck having first and second holes that extend therethrough, and independently and selectively varying a fluid pressure in each of the first and second holes between pressures above and below an ambient pressure.Type: GrantFiled: March 31, 2009Date of Patent: October 7, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Martin Liu, Chung-Yi Yu, Che Ying Hsu, Yeur-Luen Tu, Da-Hsiang Chou, Chia-Shiung Tsai
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Publication number: 20140154841Abstract: Provided is a wafer level packaging. The packaging includes a first semiconductor wafer having a transistor device and a first bonding layer that includes a first material. The packaging includes a second semiconductor wafer having a second bonding layer that includes a second material different from the first material, one of the first and second materials being aluminum-based, and the other thereof being titanium-based. Wherein a portion of the second wafer is diffusively bonded to the first wafer through the first and second bonding layers.Type: ApplicationFiled: February 6, 2014Publication date: June 5, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Richard Chu, Martin Liu, Chia-Hua Chu, Yuan-Chih Hsieh, Chung-Hsien Lin, Lan-Lin Chao, Chun-Wen Cheng, Mingo Liu
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Publication number: 20140138853Abstract: A device is described in one embodiment that includes a micro-electro-mechanical systems (MEMS) device disposed on a first substrate and a semiconductor device disposed on a second substrate. A bond electrically connects the MEMS device and the semiconductor device. The bond includes an interface between a first bonding layer including silicon on the first substrate and a second bonding layer including aluminum on the second substrate. The physical interface between the aluminum and silicon (e.g., amorphous silicon) can provide an electrical connection.Type: ApplicationFiled: January 31, 2014Publication date: May 22, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Martin Liu, Richard Chu, Hung-Hua LIn, H. T. Huang, Jung-Huei Peng, Yuan-Chih Hsieh, Lan-Lin, Chun-Wen Cheng, Chia-Shiung Tsai
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Patent number: 8648468Abstract: Provided is a wafer level packaging. The packaging includes a first semiconductor wafer having a transistor device and a first bonding layer that includes a first material. The packaging includes a second semiconductor wafer having a second bonding layer that includes a second material different from the first material, one of the first and second materials being aluminum -based, and the other thereof being titanium-based. Wherein a portion of the second wafer is diffusively bonded to the first wafer through the first and second bonding layers.Type: GrantFiled: July 29, 2010Date of Patent: February 11, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Richard Chu, Martin Liu, Chia-Hua Chu, Yuan-Chih Hsieh, Chung-Hsien Lin, Lan-Lin Chao, Chun-Wen Cheng, Mingo Liu
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Patent number: 8647962Abstract: The present disclosure provides a method of bonding a plurality of substrates. In an embodiment, a first substrate includes a first bonding layer. The second substrate includes a second bonding layer. The first bonding layer includes silicon; the second bonding layer includes aluminum. The first substrate and the second substrate are bonded forming a bond region having an interface between the first bonding layer and the second bonding layer. A device having a bonding region between substrates is also provided. The bonding region includes an interface between a layer including silicon and a layer including aluminum.Type: GrantFiled: March 23, 2010Date of Patent: February 11, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Martin Liu, Richard Chu, Hung Hua Lin, Hsin-Ting Huang, Jung-Huei Peng, Yuan-Chih Hsieh, Lan-Lin Chao, Chun-Wen Cheng, Chia-Shiung Tsai
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Patent number: 8598687Abstract: The present disclosure provides various embodiments of a via structure and method of manufacturing same. In an example, a via structure includes a via having via sidewall surfaces defined by a semiconductor substrate. The via sidewall surfaces have a first portion and a second portion. A conductive layer is disposed in the via on the first portion of the via sidewall surfaces, and a dielectric layer is disposed on the second portion of the via sidewall surfaces. The dielectric layer is disposed between the second portion of the via sidewall surfaces and the conductive layer. In an example, the dielectric layer is an oxide layer.Type: GrantFiled: May 25, 2012Date of Patent: December 3, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yuan-Chih Hsieh, Richard Chu, Ming-Tung Wu, Martin Liu, Lan-Lin Chao, Chia-Shiung Tsai
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Patent number: 8445380Abstract: The present disclosure provides various embodiments of a via structure and method of manufacturing same. In an example, a method for forming a via structure includes forming a via in a semiconductor substrate, wherein via sidewalls of the via are defined by the semiconductor substrate; forming a dielectric layer on the via sidewalls; removing the dielectric layer from a portion of the via sidewalls; and forming a conductive layer to fill the via, wherein the conductive layer is disposed over the dielectric layer and the portion of the via sidewalls. In an example, the dielectric layer is an oxide layer.Type: GrantFiled: May 25, 2012Date of Patent: May 21, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yuan-Chih Hsieh, Richard Chu, Ming-Tung Wu, Martin Liu, Lan-Lin Chao, Chia-Shiung Tsai
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Publication number: 20120235300Abstract: The present disclosure provides various embodiments of a via structure and method of manufacturing same. In an example, a via structure includes a via having via sidewall surfaces defined by a semiconductor substrate. The via sidewall surfaces have a first portion and a second portion. A conductive layer is disposed in the via on the first portion of the via sidewall surfaces, and a dielectric layer is disposed on the second portion of the via sidewall surfaces. The dielectric layer is disposed between the second portion of the via sidewall surfaces and the conductive layer. In an example, the dielectric layer is an oxide layer.Type: ApplicationFiled: May 25, 2012Publication date: September 20, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yuan-Chih Hsieh, Richard Chu, Ming-Tung Wu, Martin Liu, Lan-Lin Chao, Chia-Shiung Tsai
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Publication number: 20120238091Abstract: The present disclosure provides various embodiments of a via structure and method of manufacturing same. In an example, a method for forming a via structure includes forming a via in a semiconductor substrate, wherein via sidewalls of the via are defined by the semiconductor substrate; forming a dielectric layer on the via sidewalls; removing the dielectric layer from a portion of the via sidewalls; and forming a conductive layer to fill the via, wherein the conductive layer is disposed over the dielectric layer and the portion of the via sidewalls. In an example, the dielectric layer is an oxide layer.Type: ApplicationFiled: May 25, 2012Publication date: September 20, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yuan-Chih Hsieh, Richard Chu, Ming-Tung Wu, Martin Liu, Lan-Lin Chao, Chia-Shiung Tsai
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Patent number: 8207595Abstract: A semiconductor device includes a substrate wafer, a dielectric layer overlying the substrate wafer, a patterned conductor layer in the dielectric layer, and a first barrier layer overlying the conductor layer. A silicon top wafer is bonded to the dielectric layer. A via is formed through the top wafer and a portion of the dielectric layer to the first barrier layer. A sidewall dielectric layer is formed along inner walls of the via, adjacent the top wafer to a distance below an upper surface of the top wafer, forming a sidewall dielectric layer shoulder. A sidewall barrier layer is formed inward of the sidewall dielectric layer, lining the via from the first barrier layer to the upper surface of the top wafer. A conductive layer fills the via and a top barrier layer is formed on the conductive layer, the sidewall barrier layer, and the top wafer.Type: GrantFiled: October 5, 2010Date of Patent: June 26, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yuan-Chih Hsieh, Richard Chu, Ming-Tung Wu, Martin Liu, Lan-Lin Chao, Chia-Shiung Tsai
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Patent number: 8173518Abstract: Provided is a method of fabricating a semiconductor device. The method includes providing a device substrate having a front side, a back side, and a first edge portion, forming a material layer over a portion of the front side of the device substrate, trimming the first edge portion, removing the material layer, bonding the front side of the device substrate to a carrier substrate, thinning the device substrate from the back side, and trimming a second edge portion of the thinned device substrate.Type: GrantFiled: March 31, 2009Date of Patent: May 8, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Martin Liu, Alex Hsu, Chung-Yi Yu, Chia-Shiung Tsai
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Publication number: 20120080761Abstract: A semiconductor device includes a substrate wafer, a dielectric layer overlying the substrate wafer, a patterned conductor layer in the dielectric layer, and a first barrier layer overlying the conductor layer. A silicon top wafer is bonded to the dielectric layer. A via is formed through the top wafer and a portion of the dielectric layer to the first barrier layer. A sidewall dielectric layer is formed along inner walls of the via, adjacent the top wafer to a distance below an upper surface of the top wafer, forming a sidewall dielectric layer shoulder. A sidewall barrier layer is formed inward of the sidewall dielectric layer, lining the via from the first barrier layer to the upper surface of the top wafer. A conductive layer fills the via and a top barrier layer is formed on the conductive layer, the sidewall barrier layer, and the top wafer.Type: ApplicationFiled: October 5, 2010Publication date: April 5, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yuan-Chih Hsieh, Richard Chu, Ming-Tung Wu, Martin Liu, Lan-Lin Chao, Chia-Shiung Tsai
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Publication number: 20120025389Abstract: Provided is a wafer level packaging. The packaging includes a first semiconductor wafer having a transistor device and a first bonding layer that includes a first material. The packaging includes a second semiconductor wafer having a second bonding layer that includes a second material different from the first material, one of the first and second materials being aluminum-based, and the other thereof being titanium-based. Wherein a portion of the second wafer is diffusively bonded to the first wafer through the first and second bonding layers.Type: ApplicationFiled: July 29, 2010Publication date: February 2, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Richard Chu, Martin Liu, Chia-Hua Chu, Yuan-Chih Hsieh, Chung-Hsien Lin, Lan-Lin Chao, Chun-Wen Cheng, Mingo Liu
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Patent number: 8048807Abstract: Provided is a method for fabricating a semiconductor device that includes providing a semiconductor substrate having a front side and a backside, where active or passive devices are formed in the front side, rotating the semiconductor substrate, and etching the backside of the semiconductor substrate by introducing a first etchant while the substrate is rotated, the first etchant including an R—COOH.Type: GrantFiled: September 5, 2008Date of Patent: November 1, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming Chyi Liu, Yao Fei Chuang, Martin Liu, Gwo-Yuh Shiau, Chia-Shiung Tsai
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Publication number: 20110261590Abstract: A resonant converter comprising: a controllable current source; a resonant tank circuit coupled to the current source; and an isolated buck-type converter coupled to the resonant tank circuit, the isolated buck-type converter having an output, wherein the resonant tank circuit enables switches in the isolated buck-type converter to switch under soft-switching conditions. In some embodiments, the controllable current source is a switch-mode-type current source. In some embodiments, the isolated buck-type converter comprises a half-bridge converter. In some embodiments, the isolated buck-type converter comprises a full-bridge converter. In some embodiments, the isolated buck-type converter comprises a push-pull converter.Type: ApplicationFiled: April 22, 2010Publication date: October 27, 2011Applicant: FLEXTRONICS AP, LLCInventor: Martin Liu
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Publication number: 20110233621Abstract: The present disclosure provides a method of bonding a plurality of substrates. In an embodiment, a first substrate includes a first bonding layer. The second substrate includes a second bonding layer. The first bonding layer includes silicon; the second bonding layer includes aluminum. The first substrate and the second substrate are bonded forming a bond region having an interface between the first bonding layer and the second bonding layer. A device having a bonding region between substrates is also provided. The bonding region includes an interface between a layer including silicon and a layer including aluminum.Type: ApplicationFiled: March 23, 2010Publication date: September 29, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Martin Liu, Richard Chu, Hung-Hua Lin, H. T. Huang, Jung-Huei Peng, Yuan-Chih Hsieh, Lan-Lin Chao, Chun-Wen Cheng, Chia-Shiung Tsai
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Publication number: 20100248446Abstract: Provided is an apparatus and a method of holding a device. The apparatus includes a wafer chuck having first and second holes that extend therethrough, and a pressure control structure that can independently and selectively vary a fluid pressure in each of the first and second holes between pressures above and below an ambient pressure. The method includes providing a wafer chuck having first and second holes that extend therethrough, and independently and selectively varying a fluid pressure in each of the first and second holes between pressures above and below an ambient pressure.Type: ApplicationFiled: March 31, 2009Publication date: September 30, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Martin Liu, Chung-Yi Yu, Che Ying Hsu, Yeur-Luen Tu, Da-Hsiang Chou, Chia-Shiung Tsai