Patents by Inventor Martin Vorbach

Martin Vorbach has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210406027
    Abstract: The invention relates to a method for processing instructions out-of-order on a processor comprising an arrangement of execution units. The inventive method comprises looking up operand sources in a Register Positioning Table and setting operand input references of the instruction to be issued accordingly, checking for an Execution Unit (EXU) available for receiving a new instruction, and issuing the instruction to the available Execution Unit and entering a reference of the result register addressed by the instruction to be issued to the Execution Unit into the Register Positioning Table (RPT).
    Type: Application
    Filed: July 12, 2021
    Publication date: December 30, 2021
    Applicant: Hyperion Core, Inc.
    Inventor: Martin VORBACH
  • Publication number: 20210286755
    Abstract: Implementations relate to a data processor that includes a data processing unit having a plurality of processing elements and a cache hierarchy including a plurality of levels of data caches. The data caches include a first level data cache connected to a second level data cache, and a main memory connected to the highest level cache of the cache hierarchy. At least one of the first level data cache or second level data cache is divided into a plurality of cache segments, and during operation of the data processor, at least some of the plurality of cache segments are excluded from cache operation. Each of the excluded cache segments is dedicated to an associated processing element as tightly coupled local access memory.
    Type: Application
    Filed: October 24, 2020
    Publication date: September 16, 2021
    Applicant: Hyperion Core, Inc.
    Inventor: Martin Vorbach
  • Patent number: 11061682
    Abstract: The invention relates to a method for processing instructions out-of-order on a processor comprising an arrangement of execution units. The inventive method comprises looking up operand sources in a Register Positioning Table and setting operand input references of the instruction to be issued accordingly, checking for an Execution Unit (EXU) available for receiving a new instruction, and issuing the instruction to the available Execution Unit and entering a reference of the result register addressed by the instruction to be issued to the Execution Unit into the Register Positioning Table (RPT).
    Type: Grant
    Filed: December 13, 2015
    Date of Patent: July 13, 2021
    Inventor: Martin Vorbach
  • Patent number: 10908914
    Abstract: A single chip sequential processor comprising at least one ALU-Block, where said sequential processor is capable of maintaining its op-codes while processing data such as to overcome the necessity of requiring a new instruction in every clock cycle.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: February 2, 2021
    Assignee: Hyperion Core, Inc.
    Inventors: Martin Vorbach, Frank May, Markus Weinhardt
  • Publication number: 20210026637
    Abstract: The present invention relates to a processor having a trace cache and a plurality of ALUs arranged in a matrix, comprising an analyser unit located between the trace cache and the ALUs, wherein the analyser unit analyses the code in the trace cache, detects loops, transforms the code, and issues to the ALUs sections of the code combined to blocks for joint execution for a plurality of clock cycles.
    Type: Application
    Filed: October 14, 2020
    Publication date: January 28, 2021
    Applicant: Hyperion Core, Inc.
    Inventor: Martin VORBACH
  • Patent number: 10885996
    Abstract: A processor comprising an ALU a programmable function unit wherein the functional unit may be programmed to comprise multistage logic.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: January 5, 2021
    Assignee: PACT XPP SCHWEIZ AG
    Inventor: Martin Vorbach
  • Publication number: 20200241879
    Abstract: A single chip sequential processor comprising at least one ALU-Block, where said sequential processor is capable of maintaining its op-codes while processing data such as to overcome the necessity of requiring a new instruction in every clock cycle.
    Type: Application
    Filed: September 4, 2019
    Publication date: July 30, 2020
    Applicant: Hyperion Core, Inc.
    Inventors: Martin VORBACH, Frank MAY, Markus WEINHARDT
  • Patent number: 10579584
    Abstract: An integrated data processing core and a data processor are provided on a single integrated circuit and command sequences are forwarded from the data processing core to be executed on the array data processor wherein the command sequences comprise a group of instructions defining an algorithm.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: March 3, 2020
    Assignee: PACT XPP SCHWEIZ AG
    Inventors: Martin Vorbach, J├╝rgen Becker, Markus Weinhardt, Volker Baumgarte, Frank May
  • Publication number: 20200057749
    Abstract: An array of ALUs and a controlling and controlling unit providing the array sequentially ordered subapplications, wherein an ALU signals completion of execution of a sub application to the controlling unit, which then provides a next sequential subapplication to the requesting ALU.
    Type: Application
    Filed: August 22, 2019
    Publication date: February 20, 2020
    Inventors: Martin Vorbach, Armin Nueckel
  • Publication number: 20200042492
    Abstract: The present invention relates to a method for compiling code for a multi-core processor, comprising: detecting and optimizing a loop, partitioning the loop into partitions executable and mappable on physical hardware with optimal instruction level parallelism, optimizing the loop iterations and/or loop counter for ideal mapping on hardware, chaining the loop partitions generating a list representing the execution sequence of the partitions.
    Type: Application
    Filed: June 19, 2019
    Publication date: February 6, 2020
    Applicant: Hyperion Core, Inc.
    Inventor: Martin VORBACH
  • Publication number: 20190377580
    Abstract: A processor including an instruction fetcher to fetch instructions, a decoder to decode the instructions, at least one load unit adapted to load data, at least one execution unit adapted to perform arithmetic computations on the data by executing the fetched and decoded instructions, a register file adapted to store results of the arithmetic computations, and a multiplexer arrangement provided such that one or more units of the execution unit selectively obtain operands from one of: the register file or a unit used for arithmetic computation of a preceding instruction. The processor is adapted to process and execute the instructions such that processing of the instructions is started under the following conditions: the execution unit is ready for instruction execution, and data from the at least one load unit is available to the at least one execution unit.
    Type: Application
    Filed: February 23, 2019
    Publication date: December 12, 2019
    Applicant: Hyperion Core Inc.
    Inventors: Martin VORBACH, Frank MAY, Markus WEINHARDT
  • Patent number: 10409765
    Abstract: An array of ALUs and a controlling and controlling unit providing the array sequentially ordered subapplications, wherein an ALU signals completion of execution of a subapplication to the controlling unit, which then provides a next sequential subapplication to the requesting ALU.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: September 10, 2019
    Assignee: PACT XPP SCHWEIZ AG
    Inventors: Martin Vorbach, Armin Nuckel
  • Patent number: 10409608
    Abstract: A single chip sequential processor comprising at least one ALU-Block, where said sequential processor is capable of maintaining its op-codes while processing data such as to overcome the necessity of requiring a new instruction in every clock cycle.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: September 10, 2019
    Assignee: Hyperion Core, Inc.
    Inventors: Martin Vorbach, Frank May, Markus Weinhardt
  • Publication number: 20190197015
    Abstract: The invention relates to a multi-core processor memory system, wherein it is provided that the system comprises memory channels between the multi-core processor and the system memory, and that the system comprises at least as many memory channels as processor cores, each memory channel being dedicated to a processor core, and that the memory system relates at run-time dynamically memory blocks dedicatedly to the accessing core, the accessing core having dedicated access to the memory bank via the memory channel.
    Type: Application
    Filed: July 23, 2018
    Publication date: June 27, 2019
    Applicant: Hyperion Core, Inc.
    Inventor: Martin Vorbach
  • Patent number: 10331615
    Abstract: The present invention relates to a method for compiling code for a multi-core processor, comprising: detecting and optimizing a loop, partitioning the loop into partitions executable and mappable on physical hardware with optimal instruction level parallelism, optimizing the loop iterations and/or loop counter for ideal mapping on hardware, chaining the loop partitions generating a list representing the execution sequence of the partitions.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: June 25, 2019
    Assignee: Hyperion Core, Inc.
    Inventor: Martin Vorbach
  • Patent number: 10331194
    Abstract: A method of clocking a plurality of programmable, sequential data processing units, by adjusting the clock frequency of at least one of the programmable, sequential data processing units, without affecting the clock frequency of at least one other of the programmable, sequential data processing units.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: June 25, 2019
    Assignee: PACT XPP Schweiz AG
    Inventors: Martin Vorbach, Volker Baumgarte
  • Publication number: 20190171449
    Abstract: The present invention related to a method for compiling high-level software code into hardware, transforming each instruction into a respective hardware block and using an execution control signal representing the program pointer for triggering the execution within each respective hardware block.
    Type: Application
    Filed: January 10, 2019
    Publication date: June 6, 2019
    Applicant: Hyperion Core, Inc.
    Inventor: Martin VORBACH
  • Patent number: 10296488
    Abstract: A multi-processor having a plurality of data processing units and memory units has a bus system that selectively interconnects the processing units and the memory units.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: May 21, 2019
    Assignee: PACT XPP SCHWEIZ AG
    Inventor: Martin Vorbach
  • Publication number: 20190102173
    Abstract: At the inputs and/or outputs, memories are assigned to a reconfigurable module to achieve decoupling of internal data and in particular decoupling of the reconfiguration cycles from the external data streams (to/from peripherals, memories, etc.
    Type: Application
    Filed: November 14, 2018
    Publication date: April 4, 2019
    Inventors: Martin Vorbach, Volker Baumgarte, Frank May, Armin Nuckel
  • Publication number: 20190079769
    Abstract: The present invention relates to a processor having a trace cache and a plurality of ALUs arranged in a matrix, comprising an analyser unit located between the trace cache and the ALUs, wherein the analyser unit analyses the code in the trace cache, detects loops, transforms the code, and issues to the ALUs sections of the code combined to blocks for joint execution for a plurality of clock cycles.
    Type: Application
    Filed: September 13, 2018
    Publication date: March 14, 2019
    Applicant: Hyperion Core, Inc.
    Inventor: Martin VORBACH