Patents by Inventor Martin Vorbach

Martin Vorbach has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • TOOL-LEVEL AND HARDWARE-LEVEL CODE OPTIMIZATION AND RESPECTIVE HARDWARE MODIFICATION
    Publication number: 20190171449
    Abstract: The present invention related to a method for compiling high-level software code into hardware, transforming each instruction into a respective hardware block and using an execution control signal representing the program pointer for triggering the execution within each respective hardware block.
    Type: Application
    Filed: January 10, 2019
    Publication date: June 6, 2019
    Applicant: Hyperion Core, Inc.
    Inventor: Martin VORBACH
  • Multi-processor with selectively interconnected memory units
    Patent number: 10296488
    Abstract: A multi-processor having a plurality of data processing units and memory units has a bus system that selectively interconnects the processing units and the memory units.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: May 21, 2019
    Assignee: PACT XPP SCHWEIZ AG
    Inventor: Martin Vorbach
  • METHODS AND SYSTEMS FOR TRANSFERRING DATA BETWEEN A PROCESSING DEVICE AND EXTERNAL DEVICES
    Publication number: 20190102173
    Abstract: At the inputs and/or outputs, memories are assigned to a reconfigurable module to achieve decoupling of internal data and in particular decoupling of the reconfiguration cycles from the external data streams (to/from peripherals, memories, etc.
    Type: Application
    Filed: November 14, 2018
    Publication date: April 4, 2019
    Inventors: Martin Vorbach, Volker Baumgarte, Frank May, Armin Nuckel
  • PROVIDING CODE SECTIONS FOR MATRIX OF ARITHMETIC LOGIC UNITS IN A PROCESSOR
    Publication number: 20190079769
    Abstract: The present invention relates to a processor having a trace cache and a plurality of ALUs arranged in a matrix, comprising an analyser unit located between the trace cache and the ALUs, wherein the analyser unit analyses the code in the trace cache, detects loops, transforms the code, and issues to the ALUs sections of the code combined to blocks for joint execution for a plurality of clock cycles.
    Type: Application
    Filed: September 13, 2018
    Publication date: March 14, 2019
    Applicant: Hyperion Core, Inc.
    Inventor: Martin VORBACH
  • Array Processor Having a Segmented Bus System
    Publication number: 20190065428
    Abstract: An array processor on integrated circuit chip. The array processor has a plurality of memories and a segmented bus system, wherein each segment is selectively connectable to other segments and wherein each segment has a plurality of selectable data paths. Each processor has a processing element, an input register and an output register, each of which is connected to a segment of the segmented bus system. The segmented bus system provides a plurality of selectable data paths between each processor and other processors, between each processor and each memory and between each memory and other memories.
    Type: Application
    Filed: April 14, 2017
    Publication date: February 28, 2019
    Inventors: Martin VORBACH, Frank May, Dirk Reichardt, Frank Lier, Gerd Ehlers, Armin Nückel, Volker Baumgarte, Prashant Rao, Jens Oertel
  • Method of transferring data between external devices and an array processor
    Patent number: 10152320
    Abstract: A method for coordinating the transfer of data between external memory and an array of data processors using address generators and local memory includes loading a plurality of groups of operands into local memory, processing the plurality of groups of operands on a single processor, and then returning the processed results to the external memory.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: December 11, 2018
    Assignee: Scientia Sol Mentis AG
    Inventors: Martin Vorbach, Volker Baumgarte, Frank May, Armin Nuckel
  • Array Processor Having a Segmented Bus System
    Publication number: 20180300278
    Abstract: An array processor on integrated circuit chip. The array processor has a plurality of memories and a segmented bus system, wherein each segment is selectively connectable to other segments and wherein each segment has a plurality of selectable data paths. Each processor has a processing element, an input register and an output register, each of which is connected to a segment of the segmented bus system. The segmented bus system provides a plurality of selectable data paths between each processor and other processors, between each processor and each memory and between each memory and other memories.
    Type: Application
    Filed: April 14, 2017
    Publication date: October 18, 2018
    Applicant: PACT XPP TECHNOLOGIES AG
    Inventors: Martin VORBACH, Frank May, Dirk Reichardt, Frank Lier, Gerd Ehlers, Armin Nückel, Volker Baumgarte, Prashant Rao, Jens Oertel
  • Method for processing data
    Patent number: 10031733
    Abstract: A method for operating a system on a chip comprising a conventional processor unit (CISC, RISC, VLIW, DSP) and an array processor having a multidimensional arrangement of arithmetic units. Operation information for the array processor are stored in a memory shared between the conventional processor and the array processor. At runtime the conventional processor points the array processor to the memory area comprising the operation information. A management unit inside the array processor is autonomously loading the operation information into the array processor.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: July 24, 2018
    Assignee: Scientia Sol Mentis AG
    Inventors: Martin Vorbach, Frank May, Markus Weinhardt, Joao Manuel Paiva Cardoso
  • Parallel memory systems
    Patent number: 10031888
    Abstract: The invention relates to a multi-core processor memory system, wherein it is provided that the system comprises memory channels between the multi-core processor and the system memory, and that the system comprises at least as many memory channels as processor cores, each memory channel being dedicated to a processor core, and that the memory system relates at run-time dynamically memory blocks dedicatedly to the accessing core, the accessing core having dedicated access to the memory bank via the memory channel.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: July 24, 2018
    Assignee: Hyperion Core, Inc.
    Inventor: Martin Vorbach
  • ISSUING INSTRUCTIONS TO MULTIPLE EXECUTION UNITS
    Publication number: 20180181403
    Abstract: A single chip sequential processor comprising at least one ALU-Block, where said sequential processor is capable of maintaining its op-codes while processing data such as to overcome the necessity of requiring a new instruction in every clock cycle.
    Type: Application
    Filed: February 7, 2018
    Publication date: June 28, 2018
    Applicant: Hyperion Core, Inc.
    Inventors: Martin VORBACH, Frank MAY, Markus WEINHARDT
  • MULTI-PROCESSOR WITH SELECTIVELY INTERCONNECTED MEMORY UNITS
    Publication number: 20180067896
    Abstract: A multi-processor having a plurality of data processing units and memory units has a bus system that selectively interconnects the processing units and the memory units.
    Type: Application
    Filed: November 13, 2017
    Publication date: March 8, 2018
    Inventor: Martin Vorbach
  • Issuing instructions to multiple execution units
    Patent number: 9898297
    Abstract: A single chip sequential processor comprising at least one ALU-Block, where said sequential processor is capable of maintaining its op-codes while processing data such as to overcome the necessity of requiring a new instruction in every clock cycle.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: February 20, 2018
    Assignee: Hyperion Core, Inc.
    Inventors: Martin Vorbach, Frank May, Markus Weinhardt
  • SYSTEM AND METHOD FOR A CACHE IN A MULTI-CORE PROCESSOR
    Publication number: 20180039576
    Abstract: The invention relates to a multi-core processor system, in particular a single-package multi-core processor system, comprising at least two processor cores, preferably at least four processor cores, each of said a least two cores, preferably at least four processor core, having a local LEVEL-1 cache, a tree communication structure combining the multiple LEVEL-1 caches, the tree having at 1 a one node, preferably at least three nodes for a four processor. core multi-core processor, and TAG information is associated to data managed within the tree, usable in the treatment of the data.
    Type: Application
    Filed: July 28, 2017
    Publication date: February 8, 2018
    Applicant: Hyperion Core, Inc.
    Inventor: Martin VORBACH
  • ADVANCED PROCESSOR ARCHITECTURE
    Publication number: 20180004530
    Abstract: The invention relates to a method for processing instructions out-of-order on a processor comprising an arrangement of execution units. The inventive method comprises: 1) looking up operand sources in a Register Positioning Table and setting operand input references of the instruction to be issued accordingly; 2) checking for an Execution Unit (EXU) available for receiving a new instruction; and 3) issuing the instruction to the available Execution Unit and enter a reference of the result register addressed by the instruction to be issued to the Execution Unit into the Register Positioning Table (RPT).
    Type: Application
    Filed: December 13, 2015
    Publication date: January 4, 2018
    Inventor: Martin VORBACH
  • TOOL-LEVEL AND HARDWARE-LEVEL CODE OPTIMIZATION AND RESPECTIVE HARDWARE MODIFICATION
    Publication number: 20170364338
    Abstract: The present invention related to a method for compiling high-level software code into hardware, transforming each instruction into a respective hardware block and using an execution control signal representing the program pointer for triggering the execution within each respective hardware block.
    Type: Application
    Filed: July 7, 2017
    Publication date: December 21, 2017
    Applicant: Hyperion Core, Inc.
    Inventor: Martin VORBACH
  • Multi-processor with selectively interconnected memory units
    Patent number: 9817790
    Abstract: A multi-processor having a plurality of data processing units and memory units has a bus system that selectively interconnects the processing units and the memory units.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: November 14, 2017
    Assignee: PACT XPP TECHNOLOGIES AG
    Inventor: Martin Vorbach
  • METHOD FOR PROVIDING SUBAPPLICATIONS TO AN ARRAY OF ALUS
    Publication number: 20170286364
    Abstract: An array of ALUs and a controlling and controlling unit providing the array sequentially ordered subapplications, wherein an ALU signals completion of execution of a subapplication to the controlling unit, which then provides a next sequential subapplication to the requesting ALU.
    Type: Application
    Filed: June 21, 2017
    Publication date: October 5, 2017
    Inventors: Martin Vorbach, Armin Nuckel
  • OPTIMIZATION OF LOOPS AND DATA FLOW SECTIONS IN MULTI-CORE PROCESSOR ENVIRONMENT
    Publication number: 20170262406
    Abstract: The present invention relates to a method for compiling code for a multi-core processor, comprising: detecting and optimizing a loop, partitioning the loop into partitions executable and mappable on physical hardware with optimal instruction level parallelism, optimizing the loop iterations and/or loop counter for ideal mapping on hardware, chaining the loop partitions generating a list representing the execution sequence of the partitions.
    Type: Application
    Filed: May 22, 2017
    Publication date: September 14, 2017
    Applicant: Hyperion Core, Inc.
    Inventor: Martin VORBACH
  • System and method for a cache in a multi-core processor
    Patent number: 9734064
    Abstract: The invention relates to a multi-core processor system, in particular a single-package multi-core processor system, comprising at least two processor cores, preferably at least four processor cores, each of said a least two cores, preferably at least four processor core, having a local LEVEL-1 cache, a tree communication structure combining the multiple LEVEL-1 caches, the tree having at 1 a one node, preferably at least three nodes for a four processor. core multi-core processor, and TAG information is associated to data managed within the tree, usable in the treatment of the data.
    Type: Grant
    Filed: July 3, 2015
    Date of Patent: August 15, 2017
    Assignee: Hyperion Core, Inc.
    Inventor: Martin Vorbach
  • Tool-level and hardware-level code optimization and respective hardware modification
    Patent number: 9703538
    Abstract: The present invention relates to a method for compiling high-level software code into hardware, transforming each instruction into a respective hardware block and using an execution control signal representing the program pointer for triggering the execution within each respective hardware block.
    Type: Grant
    Filed: June 6, 2012
    Date of Patent: July 11, 2017
    Assignee: Hyperion Core, Inc.
    Inventor: Martin Vorbach