Patents by Inventor Martin Vorbach

Martin Vorbach has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods and devices for treating and processing data
    Publication number: 20170192481
    Abstract: A method of clocking a plurality of programmable, sequential data processing units, by adjusting the clock frequency of at least one of the programmable, sequential data processing units, without affecting the clock frequency of at least one other of the programmable, sequential data processing units.
    Type: Application
    Filed: January 17, 2017
    Publication date: July 6, 2017
    Applicant: PACT XPP TECHNOLOGIES AG
    Inventors: Martin Vorbach, Volker Baumgarte
  • Configurable logic integrated circuit having a multidimensional structure of configurable elements
    Patent number: 9690747
    Abstract: An array processor composed of processor cells that are programmed by a controlling unit, and that are reprogrammed when a cell has finished a current data processing operation, even while other cell continue to process data with their current programming.
    Type: Grant
    Filed: May 13, 2014
    Date of Patent: June 27, 2017
    Assignee: PACT XPP Technologies, AG
    Inventors: Martin Vorbach, Armin Nuckel
  • Optimization of loops and data flow sections in multi-core processor environment
    Patent number: 9672188
    Abstract: The present invention relates to a method for compiling code for a multi-core processor, comprising: detecting and optimizing a loop, partitioning the loop into partitions executable and mappable on physical hardware with optimal instruction level parallelism, optimizing the loop iterations and/or loop counter for ideal mapping on hardware, chaining the loop partitions generating a list representing the execution sequence of the partitions.
    Type: Grant
    Filed: April 22, 2015
    Date of Patent: June 6, 2017
    Assignee: Hyperion Core, Inc.
    Inventor: Martin Vorbach
  • Video stream evaluation
    Patent number: 9659221
    Abstract: The invention relates to a method for recognizing activities detected in video streams. In this case, it is intended that data relating to frame differences are accumulated for frame sequences in fields, gradients and/or value difference intervals are determined in the accumulator fields, and activity is concluded from the gradients.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: May 23, 2017
    Inventor: Martin Vorbach
  • Array processor having a segmented bus system
    Patent number: 9626325
    Abstract: An array processor on integrated circuit chip. The array processor has a plurality of memories and a segmented bus system, wherein each segment is selectively connectable to other segments and wherein each segment has a plurality of selectable data paths. A segment is connected to each array processor and each memory whereby a plurality of selectable data paths are provided between each processor and other processors, between each processor and each memory and between each memory and other memories.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: April 18, 2017
    Assignee: PACT XPP TECHNOLOGIES AG
    Inventors: Martin Vorbach, Frank May, Dirk Reichardt, Frank Lier, Gerd Ehlers, Armin Nückel, Volker Baumgarte, Prashant Rao, Jens Oertel
  • Multiprocessor having runtime adjustable clock and clock dependent power supply
    Patent number: 9552047
    Abstract: A multiprocessor that that provides for adjusting the clock frequency for at least some data processing units at runtime and a voltage supply adapted to supply higher supply voltages for data processing at higher clock frequencies.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: January 24, 2017
    Assignee: PACT XPP TECHNOLOGIES AG
    Inventors: Martin Vorbach, Volker Baumgarte
  • Method of Transferring Data between External Devices and an Array Processor
    Publication number: 20160357555
    Abstract: A method for coordinating the transfer of data between external memory and an array of data processors using address generators and local memory. The method includes loading a plurality of groups of operands into local memory, processing the plurality of groups of operands on a single processor, and then returning the process results external memory.
    Type: Application
    Filed: August 1, 2016
    Publication date: December 8, 2016
    Applicant: PACT XPP TECHNOLOGIES AG
    Inventors: Martin Vorbach, Volker Baumgarte, Frank May, Armin Nuckel
  • PROVIDING CODE SECTIONS FOR MATRIX OF ARITHMETIC LOGIC UNITS IN A PROCESSOR
    Publication number: 20160306631
    Abstract: The present invention relates to a processor having a trace cache and a plurality of ALUs arranged in a matrix, comprising an analyser unit located between the trace cache and the ALUs, wherein the analyser unit analyses the code in the trace cache, detects loops, transforms the code, and issues to the ALUs sections of the code combined to blocks for joint execution for a plurality of clock cycles.
    Type: Application
    Filed: April 15, 2016
    Publication date: October 20, 2016
    Applicant: Hyperion Core, Inc.
    Inventor: Martin VORBACH
  • Chip including memory element storing higher level memory data on a page by page basis
    Patent number: 9436631
    Abstract: A bus system for transferring data between parts of a multiprocessor system. The bus system is divided into a plurality of segments. Each segment is controlled by a table providing routing information. The bus system establishes communication between a sender and a receiver according to data where the data includes an identifier that identifying the source of the data transfer and/or the target of the data transfer.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: September 6, 2016
    Assignee: PACT XPP TECHNOLOGIES AG
    Inventor: Martin Vorbach
  • Methods and systems for transferring data between a processing device and external devices
    Patent number: 9411532
    Abstract: An array data processor employs a plurality of address generators for communicating between groups of the data processors and external devices. In another aspect, the data processor employs a buffer system having a plurality of pointers that allow for retransmission of data from the buffer upon transfer failure.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: August 9, 2016
    Assignee: PACT XPP Technologies AG
    Inventors: Martin Vorbach, Volker Baumgarte, Frank May, Armin Nuckel
  • Multi-processor with selectively interconnected memory units
    Publication number: 20160170925
    Abstract: A multi-processor having a plurality of data processing units and memory units has a bus system that selectively interconnects the processing units and the memory units.
    Type: Application
    Filed: February 24, 2016
    Publication date: June 16, 2016
    Applicant: PACT XPP TECHNOLOGIES AG
    Inventor: Martin Vorbach
  • Array Processor Having a Segmented Bus System
    Publication number: 20160154758
    Abstract: An array processor on integrated circuit chip. The array processor has a plurality of memories and a segmented bus system, wherein each segment is selectively connectable to other segments and wherein each segment has a plurality of selectable data paths. A segment is connected to each array processor and each memory whereby a plurality of selectable data paths are provided between each processor and other processors, between each processor and each memory and between each memory and other memories.
    Type: Application
    Filed: February 8, 2016
    Publication date: June 2, 2016
    Applicant: PACT XPP TECHNOLOGIES AG
    Inventors: Martin VORBACH, Frank May, Dirk Reichardt, Frank Lier, Gerd Ehlers, Armin Nückel, Volker Baumgarte, Prashant Rao, Jens Oertel
  • Providing code sections for matrix of arithmetic logic units in a processor
    Patent number: 9348587
    Abstract: The present invention relates to a processor having a trace cache and a plurality of ALUs arranged in a matrix, comprising an analyzer unit located between the trace cache and the ALUs, wherein the analyzer unit analyzes the code in the trace cache, detects loops, transforms the code, and issues to the ALUs sections of the code combined to blocks for joint execution for a plurality of clock cycles.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: May 24, 2016
    Assignee: Hyperion Core, Inc.
    Inventor: Martin Vorbach
  • Processor Having a Programmable Function Unit
    Publication number: 20160141050
    Abstract: A processor comprising an ALU a programmable function unit wherein the functional unit may be programmed to comprise multistage logic.
    Type: Application
    Filed: January 19, 2016
    Publication date: May 19, 2016
    Applicant: PACT XPP TECHNOLOGIES AG
    Inventor: Martin Vorbach
  • Stepwise execution of exothermic reactions with participation of carbocations
    Patent number: 9327263
    Abstract: The invention relates to a method for carrying out reactions with participation of carbocations, whereby the initial most strongly exothermic phase of the reaction is carried out at high temperature (60 to 120° C.) and short residence time (1 to 30 seconds) in a microreactor and the subsequent less exothermic phases are carried out at optionally lower temperatures in two or more residence time units with longer residence times (1 to 30 seconds).
    Type: Grant
    Filed: April 26, 2006
    Date of Patent: May 3, 2016
    Assignee: ESIM Chemicals GmbH
    Inventors: Peter Pöchlauer, Martina Kotthaus, Martin Vorbach, Martin Deak, Thomas Zich, Rolf Marr
  • Multi-processor with selectively interconnected memory units
    Patent number: 9274984
    Abstract: A multi-processor having a plurality of data processing units and memory units has a bus system that selectively interconnects the processing units and the memory units.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: March 1, 2016
    Assignee: PACT XPP TECHNOLOGIES AG
    Inventor: Martin Vorbach
  • Integrated data processing core and array data processor and method for processing algorithms
    Publication number: 20160055120
    Abstract: An integrated data processing core and a data processor are provided on a single integrated circuit and command sequences are forwarded from the data processing core to be executed on the array data processor wherein the command sequences comprise a group of instructions defining an algorithm.
    Type: Application
    Filed: October 27, 2015
    Publication date: February 25, 2016
    Applicant: PACT XPP TECHNOLOGIES AG
    Inventors: Martin Vorbach, Jürgen Becker, Markus Weinhardt, Volker Baumgarte, Frank May
  • ISSUING INSTRUCTIONS TO MULTIPLE EXECUTION UNITS
    Publication number: 20160048394
    Abstract: The present invention discloses a single chip sequential processor comprising at least one ALU-Block wherein said sequential processor is capable of maintaining its op-codes while processing data such as to overcome the necessity of requiring a new instruction in every clock cycle.
    Type: Application
    Filed: August 19, 2015
    Publication date: February 18, 2016
    Applicant: HYPERION CORE, INC.
    Inventors: Martin VORBACH, Frank MAY, Markus WEINHARDT
  • Data processor chip with flexible bus system
    Patent number: 9256575
    Abstract: A data processor chip having a two-dimensional array of arithmetic logic units and memory where the arithmetic logic units are in communication with memory units in one dimension and with other arithmetic units in a second.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: February 9, 2016
    Assignee: PACT XPP TECHNOLOGIES AG
    Inventors: Martin Vorbach, Frank May, Dirk Reichardt, Frank Lier, Gerd Ehlers, Armin Nückel, Volker Baumgarte, Prashant Rao, Jens Oertel
  • Multi-processor bus and cache interconnection system
    Patent number: 9250908
    Abstract: A multi-processor cache and bus interconnection system. A multi-processor is provided a segmented cache and an interconnection system for connecting the processors to the cache segments. An interface unit communicates to external devices using module IDs and timestamps. A buffer protocol includes a retransmission buffer and method.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: February 2, 2016
    Assignee: PACT XPP TECHNOLOGIES AG
    Inventors: Martin Vorbach, Volker Baumgarte, Frank May, Armin Nuckel