Abstract: Fabrication methods, device structures, and design structures for a bipolar junction transistor. A dielectric structure is formed that is coextensive with a single crystal semiconductor material of a substrate in an active device region. A semiconductor layer is formed that includes a single crystal section coupled with the active device region. The semiconductor layer has an edge that overlaps with a top surface of the dielectric structure. An intrinsic base layer is formed on the semiconductor layer.

Abstract: Photonic devices are created by laterally growing a semiconductor material (i.e., a localized semiconductor-on-insulator layer) over a localized buried oxide (BOX) created in a semiconductor by either a trench isolation process or thermal oxidation. In one embodiment, and after trench formation in a semiconductor substrate, the trench is filled with oxide to create a localized BOX. The top surface of the BOX is recessed to depth below the topmost surface of the semiconductor substrate to expose sidewall surfaces of the semiconductor substrate within each trench. A semiconductor material is then epitaxially grown from the exposed sidewall surfaces of the semiconductor substrate.

Abstract: Device structures for a bipolar junction transistor. The device structure includes a collector region, an intrinsic base formed on the collector region, an emitter coupled with the intrinsic base and separated from the collector by the intrinsic base, and an isolation region extending through the intrinsic base to the collector region. The isolation region is formed with a first section having first sidewalls that extend through the intrinsic base and a second section with second sidewalls that extend into the collector region. The second sidewalls are inclined relative to the first sidewalls. The isolation region is positioned in a trench that is formed with first and second etching process in which the latter etches different crystallographic directions of a single-crystal semiconductor material at different etch rates.

Abstract: A method of protecting a CMOS device within an integrated photonic semiconductor structure is provided. The method may include depositing a conformal layer of germanium over the CMOS device and an adjacent area to the CMOS device, depositing a conformal layer of dielectric hardmask over the germanium, and forming, using a mask level, a patterned layer of photoresist for covering the CMOS device and a photonic device formation region within the adjacent area. Openings are etched into areas of the deposited layer of silicon nitride not covered by the patterned photoresist, such that the areas are adjacent to the photonic device formation region. The germanium material is then etched from the conformal layer of germanium at a location underlying the etched openings for forming the photonic device at the photonic device formation region. The conformal layer of germanium deposited over the CMOS device protects the CMOS device.

Abstract: Fabrication methods, device structures, and design structures for a heterojunction bipolar transistor. A collector is formed in a semiconductor substrate, an intrinsic base is formed on the semiconductor substrate, and an extrinsic base is formed on the intrinsic base. An airgap is located vertically between the extrinsic base and the collector. A contact surface is located adjacent to the airgap. The contact surface is coupled with the collector. A spacer is located laterally between the airgap and the subcollector contact surface.

Abstract: A method of protecting a CMOS device within an integrated photonic semiconductor structure is provided. The method may include depositing a conformal layer of germanium over the CMOS device and an adjacent area to the CMOS device, depositing a conformal layer of dielectric hardmask over the germanium, and forming, using a mask level, a patterned layer of photoresist for covering the CMOS device and a photonic device formation region within the adjacent area. Openings are etched into areas of the deposited layer of silicon nitride not covered by the patterned photoresist, such that the areas are adjacent to the photonic device formation region. The germanium material is then etched from the conformal layer of germanium at a location underlying the etched openings for forming the photonic device at the photonic device formation region. The conformal layer of germanium deposited over the CMOS device protects the CMOS device.

Abstract: Photonic devices are created by laterally growing a semiconductor material (i.e., a localized semiconductor-on-insulator layer) over a localized buried oxide (BOX) created in a semiconductor by either a trench isolation process or thermal oxidation. In one embodiment, and after trench formation in a semiconductor substrate, the trench is filled with oxide to create a localized BOX. The top surface of the BOX is recessed to depth below the topmost surface of the semiconductor substrate to expose sidewall surfaces of the semiconductor substrate within each trench. A semiconductor material is then epitaxially grown from the exposed sidewall surfaces of the semiconductor substrate.

Abstract: Fabrication methods, device structures, and design structures for a bipolar junction transistor. The device structure includes a collector region, an intrinsic base formed on the collector region, an emitter coupled with the intrinsic base and separated from the collector by the intrinsic base, and an isolation region extending through the intrinsic base to the collector region. The isolation region is formed with a first section having first sidewalls that extend through the intrinsic base and a second section with second sidewalls that extend into the collector region. The second sidewalls are inclined relative to the first sidewalls. The isolation region is positioned in a trench that is formed with first and second etching process in which the latter etches different crystallographic directions of a single-crystal semiconductor material at different etch rates.

Abstract: A method of forming an integrated photonic semiconductor structure having a photonic device and a CMOS device may include depositing a first silicon nitride layer having a first stress property over the photonic device, depositing an oxide layer having a stress property over the deposited first silicon nitride layer, and depositing a second silicon nitride layer having a second stress property over the oxide layer. The deposited first silicon nitride layer, the oxide layer, and the second silicon nitride layer encapsulate the photonic device.

Abstract: Fabrication methods, device structures, and design structures for a heterojunction bipolar transistor. A trench isolation region and a collector are formed in a semiconductor substrate. The collector is coextensive with the trench isolation region. A first semiconductor layer is formed that includes a of single crystal section disposed on the collector and on the trench isolation region. A second semiconductor layer is formed that includes a single crystal section disposed on the single crystal section of the first semiconductor layer and that has an outer edge that overlies the trench isolation region. The section of the first semiconductor layer has a second width greater than a first width of the collector. The section of the second semiconductor layer has a third width greater than the second width. A cavity extends laterally from the outer edge of section of the second semiconductor layer to the section of the first semiconductor layer.

Abstract: Fabrication methods, device structures, and design structures for a heterojunction bipolar transistor. A collector is formed in a semiconductor substrate, an intrinsic base is formed on the semiconductor substrate, and an extrinsic base is formed on the intrinsic base. An airgap is located vertically between the extrinsic base and the collector. A contact surface is located adjacent to the airgap. The contact surface is coupled with the collector. A spacer is located laterally between the airgap and the subcollector contact surface.

Abstract: A method of forming an integrated photonic semiconductor structure having a photonic device and adjacent CMOS devices may include depositing a first silicon nitride layer over the adjacent CMOS devices and depositing an oxide layer over the first silicon nitride layer, wherein the oxide layer conformally covers the first silicon nitride layer and the underlying adjacent CMOS devices to form a substantially planarized surface over the adjacent CMOS devices. A second silicon nitride layer is then deposited over the oxide layer and a region corresponding to forming the photonic device. A germanium layer is deposited over the oxide layer and the region corresponding to forming the photonic device. The germanium layer deposited over the adjacent CMOS devices is etched to form a germanium active layer within the photonic region, whereby the oxide layer and the second silicon nitride layer protect the adjacent CMOS devices during the etching of the germanium.

Abstract: A sensor for biomolecules includes a silicon fin comprising undoped silicon; a source region adjacent to the silicon fin, the source region comprising heavily doped silicon; a drain region adjacent to the silicon fin, the drain region comprising heavily doped silicon of a doping type that is the same doping type as that of the source region; and a layer of a gate dielectric covering an exterior portion of the silicon fin between the source region and the drain region, the gate dielectric comprising a plurality of antibodies, the plurality of antibodies configured to bind with the biomolecules, such that a drain current flowing between the source region and the drain region varies when the biomolecules bind with the antibodies.

Abstract: Device structures, fabrication methods, and design structures for a bipolar junction transistor. A first isolation region is formed in a substrate to define a lateral boundary for an active device region and an intrinsic base layer is formed on the substrate. The intrinsic base layer has a section overlying the active device region. After the intrinsic base layer is formed, the first isolation region is partially removed adjacent to the active device region to define a trench that is coextensive with the substrate in the active device region and that is coextensive with the first isolation region. The trench is at least partially filled with a dielectric material to define a second isolation region.

Abstract: Device structures, fabrication methods, and design structures for a bipolar junction transistor. A first isolation region is formed in a substrate to define a lateral boundary for an active device region and an intrinsic base layer is formed on the substrate. The intrinsic base layer has a section overlying the active device region. After the intrinsic base layer is formed, the first isolation region is partially removed adjacent to the active device region to define a trench that is coextensive with the substrate in the active device region and that is coextensive with the first isolation region. The trench is at least partially filled with a dielectric material to define a second isolation region.

Abstract: A method of protecting a CMOS device within an integrated photonic semiconductor structure is provided. The method may include depositing a conformal layer of germanium over the CMOS device and an adjacent area to the CMOS device, depositing a conformal layer of dielectric hardmask over the germanium, and forming, using a mask level, a patterned layer of photoresist for covering the CMOS device and a photonic device formation region within the adjacent area. Openings are etched into areas of the deposited layer of silicon nitride not covered by the patterned photoresist, such that the areas are adjacent to the photonic device formation region. The germanium material is then etched from the conformal layer of germanium at a location underlying the etched openings for forming the photonic device at the photonic device formation region. The conformal layer of germanium deposited over the CMOS device protects the CMOS device.

Abstract: Fabrication methods, device structures, and design structures for a heterojunction bipolar transistor. A trench isolation region and a collector are formed in a semiconductor substrate. The collector is coextensive with the trench isolation region. A first semiconductor layer is formed that includes a of single crystal section disposed on the collector and on the trench isolation region. A second semiconductor layer is formed that includes a single crystal section disposed on the single crystal section of the first semiconductor layer and that has an outer edge that overlies the trench isolation region. The section of the first semiconductor layer has a second width greater than a first width of the collector. The section of the second semiconductor layer has a third width greater than the second width. A cavity extends laterally from the outer edge of section of the second semiconductor layer to the section of the first semiconductor layer.

Abstract: Fabrication methods, device structures, and design structures for a heterojunction bipolar transistor. A trench isolation region and a collector are formed in a semiconductor substrate. The collector is coextensive with the trench isolation region. A first semiconductor layer is formed that includes a of single crystal section disposed on the collector and on the trench isolation region. A second semiconductor layer is formed that includes a single crystal section disposed on the single crystal section of the first semiconductor layer and that has an outer edge that overlies the trench isolation region. The section of the first semiconductor layer has a second width greater than a first width of the collector. The section of the second semiconductor layer has a third width greater than the second width. A cavity extends laterally from the outer edge of section of the second semiconductor layer to the section of the first semiconductor layer.

Abstract: Fabrication methods, device structures, and design structures for a heterojunction bipolar transistor. A trench isolation region and a collector are formed in a semiconductor substrate. The collector is coextensive with the trench isolation region. A first semiconductor layer is formed that includes a of single crystal section disposed on the collector and on the trench isolation region. A second semiconductor layer is formed that includes a single crystal section disposed on the single crystal section of the first semiconductor layer and that has an outer edge that overlies the trench isolation region. The section of the first semiconductor layer has a second width greater than a first width of the collector. The section of the second semiconductor layer has a third width greater than the second width. A cavity extends laterally from the outer edge of section of the second semiconductor layer to the section of the first semiconductor layer.

Abstract: Disclosed are bipolar devices, which incorporate an entirely monocrystalline link-up region between the intrinsic and extrinsic base layers, and methods of forming the devices. In the methods, a selective epitaxial deposition process grows monocrystalline semiconductor material for the extrinsic base layer on an exposed edge portion of a monocrystalline section of an intrinsic base layer. This deposition process is continued to intentionally overgrow the monocrystalline semiconductor material until it grows laterally and essentially covers a dielectric landing pad on a center portion of that same monocrystalline section of the intrinsic base layer. Subsequently, an opening is formed through the extrinsic base layer to the dielectric landing pad and the dielectric landing pad is selectively removed, thereby exposing monocrystalline surfaces only of the intrinsic and extrinsic base layers.