Abstract: A valve timing control apparatus includes a driving-side rotating member, a driven-side rotating member, a fluid pressure chamber formed by the driving-side rotating member and the driven-side rotating member and divided into a retarded angle chamber and an advanced angle chamber by a parting portion, a fluid control valve mechanism controlling a supply and a discharge of an operation fluid to and from the fluid pressure chamber, a lock mechanism locking a relative rotational phase of the driven-side rotating member relative to the driving-side rotating member at a predetermined phase, a monitoring mechanism monitoring a driving state of an internal combustion engine, and a phase setting mechanism controlling the fluid control valve mechanism so as to establish the predetermined phase in a case where the monitoring mechanism detects a signal indicating a likelihood of a decrease of a number of rotations of the internal combustion engine exceeding a control range.

Abstract: Embodiments of the disclosure provide systems and methods for clock duty cycle measurement. A clock signal and a complement of the clock signal are provided to a charge pump during first and second predetermined timing windows. A charge pump is operable to generate first and second output voltages in response to the clock signal and the complement of the clock signal during the first and second timing windows, respectively. In addition a predetermined positive voltage and a ground voltage are applied to the charge pump during predetermined third and fourth timing windows, respectively. The charge pump is operable to generate third and fourth output voltage signals corresponding to the predetermined positive and ground voltages during the third and fourth timing windows, respectively. The first, second, third and fourth voltages are then used to calculate the duty cycle of the clock.

Abstract: A design structure for a circuit for measuring the absolute duty cycle of a signal, is provided. A non-inverted path from a signal source is selected and various DCC circuit setting indices are cycled through until a divider, coupled to the output of the DCC circuit, fails. A first minimum pulse width at which the divider fails is then determined based on the index value of the DCC circuit at the time of the failure. An inverted path from the signal source is selected and the various DCC circuit setting indices are cycled through again until the divider fails. A second minimum pulse width at which the divider fails is then determined based on the index value of the DCC circuit at the time of this second failure. The duty cycle is then calculated based on a difference of the first and second minimum pulse width values.

Abstract: A valve timing control apparatus includes a driving-side rotating member, a driven-side rotating member, a fluid pressure chamber defined by the driving-side rotating member and the driven-side rotating member and divided into a retarded angle chamber and an advanced angle chamber by a parting portion, an angle detecting portion detecting a relative angle of the driven-side rotating member relative to the driving-side rotating member, a fluid control mechanism controlling a supply and a discharge of an operation fluid to and from the fluid pressure chamber, an acceleration operation quantity detecting mechanism detecting an acceleration operation quantity, and a control portion setting either a normal drive mode or an acceleration drive mode as a control mode relative to the fluid control mechanism based on the acceleration operation quantity, and controlling the fluid control mechanism so that the relative angle corresponds to a target angle determined based on the set control mode.

Abstract: According to an embodiment, a voltage-current converter circuit includes a first current mirror circuit, a first transistor, a variable resistor, a second transistor and a first current output unit. The first current mirror circuit includes a first conductivity type transistor supplied with a first voltage, and the first current mirror circuit is configured to produce a second electric current based on a first electric current. The first transistor has a second conductivity type, and the first electric current flows through the first transistor. One end of the variable resistor is connected to a source of the first transistor, the other end of the variable resistor is supplied with a second voltage, and a resistance value of the variable resistor changes depending on an input control voltage. The second transistor has the second conductivity type, and the second electric current flows through the second transistor.

Abstract: Systems and methods for enabling the determination of voltage controlled oscillator (VCO) linearity, duty cycle determination and duty cycle correction in phase locked loop circuits (PLL's.) One embodiment comprises a method including the steps of determining the frequency response of a PLL's VCO as a function of duty cycle, applying a signal based on the VCO output to the VCO input, measuring the resulting frequency of the VCO output signal, determining the duty cycle corresponding to the measured frequency, and configuring a duty cycle correction unit correct the duty cycle of the VCO output signal to about 50%. Determining the frequency response of the VCO may include, for each of several different duty cycle values between 0% and 100%, applying the VCO input signal to the VCO and determining the corresponding frequency of the VCO output signal. This may also be done for duty cycles of 0% and 100%.

Abstract: Disclosed is a valve timing control apparatus capable of avoiding inadvertent realization of a locked state by effectively preventing pulsating pressure of fluid generated in association with torque variation of a cam shaft from having any effect on a fluid passageway used for lock releasing.

Abstract: A design structure for a programmable interpolative voltage controlled oscillator (VCO) with adjustable frequency range output is provided. Programmable delay cells whose size is modifiable based on control inputs to the programmable delay cells are utilized. A different set of control inputs may be provided to programmable delay cells of an inner sub-ring from the set of control inputs provided to programmable delay cells of a main ring of the VCO. The minimum frequency output of the VCO is governed by the main ring programmable delay cell strength with the maximum frequency output of the VCO being governed by a ratio of strengths of the main ring programmable delay cells to the inner sub-ring programmable delay cell. By modifying the control inputs to the inner sub-ring and main ring programmable delay cells, the minimum and maximum frequency outputs, and thus the range between these two frequency outputs, are made programmable.

Abstract: Systems and methods for enabling the determination of voltage controlled oscillator (VCO) linearity, duty cycle determination and duty cycle correction in phase locked loop circuits (PLL's.) One embodiment comprises a method including the steps of determining the frequency response of a PLL's VCO as a function of duty cycle, applying a signal based on the VCO output to the VCO input, measuring the resulting frequency of the VCO output signal, determining the duty cycle corresponding to the measured frequency, and configuring a duty cycle correction unit correct the duty cycle of the VCO output signal to about 50%. Determining the frequency response of the VCO may include, for each of several different duty cycle values between 0% and 100%, applying the VCO input signal to the VCO and determining the corresponding frequency of the VCO output signal. This may also be done for duty cycles of 0% and 100%.

Abstract: Systems and methods for increasing the frequency range of an output signal generated by a VCO, where one or more variable delay units are incorporated into an interpolative VCO to decrease the minimum frequency at which the VCO oscillates. In one embodiment, the VCO includes a ring of serially connected inverters, a set of bypass circuits and a set of variable delay units. The bypass circuits are coupled to the ring of serially connected inverters to bypass one or more of the serially connected inverters when enabled. Each variable delay unit delays signal transitions at the input of a corresponding one of the serially connected inverters by a variable amount. The variable delay units may be positioned in series with the ring of inverters, in parallel with the bypass paths, or in parallel with corresponding inverters in the ring of inverters.

Abstract: A design structure for a circuit for measuring the absolute duty cycle of a signal anywhere on an integrated circuit device is provided. The circuit has a plurality of substantially identical pulse shaper elements, each of which expand the pulse of an input signal whose duty cycle is to be measured by a same amount. The outputs of the pulse shaper elements may be coupled to substantially identical divider circuits whose outputs are coupled to a multiplexer that selects two inputs for output to a set of master/slave configured flip-flops, one input serving as a clock and the other as data to the flip-flops. The flip-flops sample the divider outputs selected by the multiplexer to detect if the dividers have failed or not. The outputs of the flip-flops are provided to an XOR gate which outputs a duty cycle signal indicative of the duty cycle of the input signal.

Abstract: A mechanism for measuring the absolute duty cycle of a signal is provided. A non-inverted path from a signal source is selected and various DCC circuit setting indices are cycled through until a divider, coupled to the output of the DCC circuit, fails. A first minimum pulse width at which the divider fails is then determined based on the index value of the DCC circuit at the time of the failure. An inverted path from the signal source is selected and the various DCC circuit setting indices are cycled through again until the divider fails. A second minimum pulse width at which the divider fails is then determined based on the index value of the DCC circuit at the time of this second failure. The duty cycle is then calculated based on a difference of the first and second minimum pulse width values.

Abstract: A mechanism is provided for measuring the absolute duty cycle of a signal anywhere on an integrated circuit device. The mechanism employs a circuit having a plurality of substantially identical pulse shaper elements, each of which expand the pulse of an input signal whose duty cycle is to be measured by a same amount. The outputs of the pulse shaper elements may be coupled to substantially identical divider circuits whose outputs are coupled to a multiplexer that selects two inputs for output to a set of master/slave configured flip-flops, one input serving as a clock and the other as data to the flip-flops. The flip-flops sample the divider outputs selected by the multiplexer to detect if the dividers have failed or not. The outputs of the flip-flops are provided to an XOR gate which outputs a duty cycle signal indicative of the duty cycle of the input signal.

Abstract: A charge pump that includes cascode transistors and current mirror circuitry to form a folded cascode structure that isolates the control inputs from the charge pump output and also increases the range of the output. The charge pump includes inputs to receive UP and DN (down) control signals and provides an output current that is based on the control signals. The charge pump may be configured as either a differential or non-differential device. The switching transistors that receive the control signals may use a lower voltage than the current source transistors in the charge pump In differential-type embodiments of the present charge pump, an amplifier can be used to control current source transistors based on differences between the output voltages of the charge pump, thereby adjusting the current flowing through the current source transistors and driving the average of the output voltages to a desired common mode voltage.

Abstract: Mechanisms are provided for compensating for process and temperature variations in a circuit. The mechanisms may select at least one resistor in a plurality of resistors in the circuit to provide a resistance value for generating a calibration voltage input to the circuit to compensate for variations in process. A reference signal may be compared to a feedback signal generated by the circuit based on the calibration signal. A determination is made as to whether the feedback signal is within a tolerance of the reference signal and, if so, an identifier of the selected at least one resistor is stored in a memory device coupled to the circuit. The circuit may be operated using the selected at least one resistor based on the identifier stored in the memory device. An apparatus and integrated circuit device utilizing these mechanisms are also provided.

Abstract: Systems and methods for detecting the mode (a.k.a., state) of a fuse or set of fuses in a device such as an integrated circuit. One embodiment comprises a method for determining three fuse states (uncut, cut, and destroyed) by comparing the fuse voltage with two reference voltages. Each fuse state has a different (indicative) impedance and is associated with a fuse voltage. The fuse voltage is below, between, or above two reference voltages, thereby determining the fuse state. One embodiment includes the fuse in series with a read transistor as well as two reference voltage generators, each comprising a resistor and a transistor (equivalent to the read transistor). Both resistors' impedances are greater than the uncut fuse impedance and one is less than the cut fuse impedance. Two comparators are used to bracket the fuse voltage, indicating that the fuse is uncut, cut, or destroyed.

Abstract: A charge pump that includes cascade transistors and current mirror circuitry to form a folded cascade structure that isolates the control inputs from the charge pump output and also increases the range of the output. The charge pump includes inputs to receive UP and DN (down) control signals and provides an output current that is based on the control signals. The charge pump may be configured as either a differential or non-differential device. The switching transistors that receive the control signals may use a lower voltage than the current source transistors in the charge pump In differential-type embodiments of the present charge pump, an amplifier can be used to control current source transistors based on differences between the output voltages of the charge pump, thereby adjusting the current flowing through the current source transistors and driving the average of the output voltages to a desired common mode voltage.

Abstract: A communication quality management equipment connected via a control line to a plurality of wireless base stations within a wireless access network, acquires quality information of a wireless line at a present position of a mobile terminal, resource information as to a wireless line of each of the wireless base stations, and use information as to a network line of each of the wireless base stations from the respective wireless base stations in a periodic manner, or in response to an instruction issued from the communication quality management equipment, and then judges a communication quality at each of the present positions of the mobile terminal; forms communication quality map information in which the judged communication qualities have been defined in correspondence with the positional information, and transmits the formed communication quality map information to the mobile terminal in accordance with a request from the mobile terminal.

Abstract: Systems and methods for increasing the frequency range of an output signal generated by a VCO, where one or more variable delay units are incorporated into an interpolative VCO to decrease the minimum frequency at which the VCO oscillates. In one embodiment, the VCO includes a ring of serially connected inverters, a set of bypass circuits and a set of variable delay units. The bypass circuits are coupled to the ring of serially connected inverters to bypass one or more of the serially connected inverters when enabled. Each variable delay unit delays signal transitions at the input of a corresponding one of the serially connected inverters by a variable amount. The variable delay units may be positioned in series with the ring of inverters, in parallel with the bypass paths, or in parallel with corresponding inverters in the ring of inverters.

Abstract: Systems and methods for enabling the determination of voltage controlled oscillator (VCO) linearity, duty cycle determination and duty cycle correction in phase locked loop circuits (PLL's.) One embodiment comprises a method including the steps of determining the frequency response of a PLL's VCO as a function of duty cycle, applying a signal based on the VCO output to the VCO input, measuring the resulting frequency of the VCO output signal, determining the duty cycle corresponding to the measured frequency, and configuring a duty cycle correction unit correct the duty cycle of the VCO output signal to about 50%. Determining the frequency response of the VCO may include, for each of several different duty cycle values between 0% and 100%, applying the VCO input signal to the VCO and determining the corresponding frequency of the VCO output signal. This may also be done for duty cycles of 0% and 100%.