Abstract: A solid-state imaging apparatus according to the present invention is characterized in that a reset gate voltage VresH to be applied to a gate of a reset MOS transistor is lower than a power supply voltage SVDD of a power supply to which drains of an amplifying MOS transistor and the reset MOS transistor are connected.

Abstract: It is disclosed that, as an embodiment, a test circuit includes a test signal supply unit configured to supply a test signal via a signal line to signal receiving units provided in a plurality of columns, wherein the test signal supply unit is a voltage buffer or a current buffer, and the test circuit has a plurality of test signal supply units and a plurality of signal lines, and wherein at least one test signal supply unit is electrically connected to one signal line different from a signal line to which another test signal supply unit is electrically connected.

Abstract: An amplification-type solid-state imaging device supplies a voltage of VRESL1 to a gate of a reset transistor when a signal of a vertical output line is read out and supplies a voltage of VRESL2, which is greater than VRESL1, when the signal charge accumulated in a photodiode is transferred to an FD so that, via a capacitor provided between the gate of the reset transistor and the FD, good linearity is obtained by decreasing the voltage of the FD when the signal is read out and the maximum amount of charge which can be transferred is increased by increasing the voltage of the FD when the charge is transferred.

Abstract: A solid-state imaging apparatus according to the present invention is characterized in that a reset gate voltage VresH to be applied to a gate of a reset MOS transistor is lower than a power supply voltage SVDD of a power supply to which drains of an amplifying MOS transistor and the reset MOS transistor are connected.