Abstract: In a method of producing a multi-terminal type laminated ceramic electronic component in which internal electrodes are embedded in a sintered ceramic member, and the internal electrodes have plural first lead-out electrodes led out to a first side surface and plural second lead-out electrodes led out to a second side surface, the plural second lead-out electrodes of one of the adjacent internal electrodes in each internal electrode pattern are not continuous with the plural first lead-out electrodes of the other of the adjacent internal electrodes, and the plural second lead-out electrodes and the plural first lead-out electrodes are alternately arranged in a direction that is substantially perpendicular to the direction of a line connecting the first and second side surfaces.

Abstract: An apparatus is provided for packaging a laminated capacitor made to have a low ESL value and is used for a decoupling capacitor to be connected to a power supply circuit for a MPU chip providing a MPU. The laminated capacitor is accommodated within a cavity provided on a wiring board. The capacitor includes a plurality of first external terminal electrodes connected to first internal electrodes via a plurality of first feedthrough conductors and a plurality of second external terminal electrodes connected to second internal electrodes via a plurality of second feedthrough conductors. The first external terminal electrodes provided on a first major surface of a capacitor body are connected to via-hole conductors at the hot side for the power source within a substrate, and the second external terminal electrodes provided on first and second major surfaces are connected to grounding via-hole conductors and a mother board within the substrate.

Abstract: Watermark data that indicate additional information, such as copyright information, are optimized in accordance with the contents of object data, and the watermark data is embedded in image data. An image divider 200 divides image data Vi into image blocks Iij, and corresponds a selected basic pattern Phij with each of the image blocks Iij. Orthogonal transformation units 24 and 202 generate DFT coefficients I?ij and P?hij, and power element calculators 208 and 264 generate power elements I?ij and P?ij. A basic pattern adjustment unit 26 adjusts the coefficient of P?hij to generate P?hij1 to P?hijn. A watermark pattern generator 28 calculates variations before and after P?hij1 to P?hijn are embedded in I?ij, and selects, from P?hij1 to P?hijn, P??hij1 to P??hij1 that provide variations equal to or smaller than the threshold value e. Then, the watermark pattern generator 28 selects, as a watermark pattern P?ij, the pattern that is most easily detectable, and a pattern embedding unit 204 that adds P?ij to I?ij.

Abstract: A method and system is provided for assigning programs in a workflow to one or more nodes for execution. Prior to the assignment, a priority of execution of each program is calculated in relation to its dependency upon data received and transmitted data. Based upon the calculated priority and the state of each of the nodes, the programs in the workflow are dynamically assigned to one or more nodes for execution. In addition to the node assignment based upon priority, preemptive execution of the programs in the workflow is determined so that the programs in the workflow may not preemptively be executed at a selected node in response to the determination.

Abstract: An interface device in accordance with the present claimed invention is an interface device 4 that intervenes between a measuring means 2 that measures brain activities of a subject H and an object 31 to be controlled, and that comprises a reference signal storing part D1 that stores a brain activity signal measured at a time when the subject H conducts predetermined thinking different from direct thinking in order to control the object 31 to be controlled in a desired mode as a reference signal, a discriminating part 41 that compares the brain activity signal measured by the measuring means 2 with the reference signal and discriminates whether or not the thinking of the subject H is the predetermined thinking, and a controlling part 42 that controls the object 31 to be controlled in the desired mode when the discriminating part 41 discriminates that the thinking of the subject H is the predetermined thinking.

Abstract: The present invention provides methods, apparatus and systems for embedding and detecting an electronic watermark without requiring signals for geometric compensation. A particular embodiment uses a periodic pattern with repetition as an embedded pattern itself, which has information embedded as an electronic watermark, and observes the change of its period upon detection to calculate the scaling factor. When detecting the electronic watermark, the scaling factor of images is calculated from digital data that underwent the scaling processing, and then the processing to detect the electronic watermark is performed based on the obtained scaling factor.

Abstract: A first laminate block including inner conductors is manufactured, and thin holes are formed in the first laminate block so as to extend between top and bottom surfaces of the first laminate block. The thin holes are filled with conductive paste to form via holes. Then, a ceramic sheet layer is laminated on the bottom surface of the first laminate block, and a second laminate block including inner conductors is laminated on the bottom surface of the ceramic sheet layer to obtain a laminate body. Then, thin holes are formed in the laminate body so as to extend between top and bottom surfaces of the laminate body, and are filled with conductive paste to obtain through via hole.

Abstract: A multi-layer capacitor includes first and second side-surface terminal electrodes alternately arranged on four side surfaces of a capacitor body. First and second major-surface terminal electrodes are arranged on a major surface of the capacitor body. First and second internal electrodes which are opposed to each other within the capacitor body are respectively electrically connected at ends thereof to the first and second side-surface terminal electrodes, and are also respectively electrically connected to the first and second major-surface terminal electrodes through via hole conductors. With this arrangement, the directions of the currents flowing within the multi-layer capacitor are diversified, and the lengths of current-carrying paths are shortened so as to achieve a very low ESL value.

Abstract: In a method of producing a multi-terminal type laminated ceramic electronic component in which internal electrodes are embedded in a sintered ceramic member, and the internal electrodes have plural first lead-out electrodes led out to a first side surface and plural second lead-out electrodes led out to a second side surface, the plural second lead-out electrodes of one of the adjacent internal electrodes in each internal electrode pattern are not continuous with the plural first lead-out electrodes of the other of the adjacent internal electrodes, and the plural second lead-out electrodes and the plural first lead-out electrodes are alternately arranged in a direction that is substantially perpendicular to the direction of a line connecting the first and second side surfaces.

Abstract: A multi-layer capacitor includes first and second side-surface terminal electrodes alternately arranged on four side surfaces of a capacitor body. First and second major-surface terminal electrodes are arranged on a major surface of the capacitor body. First and second internal electrodes which are opposed to each other within the capacitor body are respectively electrically connected at ends thereof to the first and second side-surface terminal electrodes, and are also respectively electrically connected to the first and second major-surface terminal electrodes through via hole conductors. With this arrangement, the directions of the currents flowing within the multi-layer capacitor are diversified, and the lengths of current-carrying paths are shortened so as to achieve a very low ESL value.

Abstract: [Object]To provide lossless embedding of a visible watermark in compressed motion picture data.

Abstract: A laminated capacitor has an end surface pitch Pe, which defines an interval between adjacent first and second external terminal electrodes disposed on end surfaces having shorter sides in a body of a laminated capacitor, which is equal to or less than about 0.9 times of a side-surface pitch Ps, which defines an interval between adjacent first and second external terminal electrodes disposed on side surfaces having longer sides, in order to enhance the effect of magnetic-flux cancellation at the end surfaces and to reduce the equivalent series inductance of the whole laminated capacitor.

Abstract: A circuit substrate includes resistive films are disposed on the surfaces of lands included in a circuit pattern and these resistive films are used as resistances connected in series to a capacitor. Therefore, the resistances are connected in series without increasing the inductance in the capacitor, and accordingly, a circuit having a small impedance variation with respect to frequency can be obtained. Therefore, it is possible to obtain a power supply circuit and so forth having stable operation and fast response.

Abstract: A laminated capacitor has an end surface pitch Pe, which defines an interval between adjacent first and second external terminal electrodes disposed on end surfaces having shorter sides in a body of a laminated capacitor, which is equal to or less than about 0.9 times of a side-surface pitch Ps, which defines an interval between adjacent first and second external terminal electrodes disposed on side surfaces having longer sides, in order to enhance the effect of magnetic-flux cancellation at the end surfaces and to reduce the equivalent series inductance of the whole laminated capacitor.

Abstract: A multi-layer capacitor includes first and second side-surface terminal electrodes alternately arranged on four side surfaces of a capacitor body. First and second major-surface terminal electrodes are arranged on a major surface of the capacitor body. First and second internal electrodes which are opposed to each other within the capacitor body are respectively electrically connected at ends thereof to the first and second side-surface terminal electrodes, and are also respectively electrically connected to the first and second major-surface terminal electrodes through via hole conductors. With this arrangement, the directions of the currents flowing within the multi-layer capacitor are diversified, and the lengths of current-carrying paths are shortened so as to achieve a very low ESL value.

Abstract: An apparatus is provided for packaging a laminated capacitor made to have a low ESL value and is used for a decoupling capacitor to be connected to a power supply circuit for a MPU chip providing a MPU. The laminated capacitor is accommodated within a cavity provided on a wiring board. The capacitor includes a plurality of first external terminal electrodes connected to first internal electrodes via a plurality of first feedthrough conductors and a plurality of second external terminal electrodes connected to second internal electrodes via a plurality of second feedthrough conductors. The first external terminal electrodes provided on a first major surface of a capacitor body are connected to via-hole conductors at the hot side for the power source within a substrate, and the second external terminal electrodes provided on first and second major surfaces are connected to grounding via-hole conductors and a mother board within the substrate.

Abstract: An apparatus is provided for packaging a laminated capacitor made to have a low ESL value and is used for a decoupling capacitor to be connected to a power supply circuit for a MPU chip providing a MPU. The laminated capacitor is accommodated within a cavity provided on a wiring board. The capacitor includes a plurality of first external terminal electrodes connected to first internal electrodes via a plurality of first feedthrough conductors and a plurality of second external terminal electrodes connected to second internal electrodes via a plurality of second feedthrough conductors. The first external terminal electrodes provided on a first major surface of a capacitor body are connected to via-hole conductors at the hot side for the power source within a substrate, and the second external terminal electrodes provided on first and second major surfaces are connected to grounding via-hole conductors and a mother board within the substrate.

Abstract: An apparatus is provided for packaging a laminated capacitor made to have a low ESL value and is used for a decoupling capacitor to be connected to a power supply circuit for a MPU chip providing a MPU. The laminated capacitor is accommodated within a cavity provided on a wiring board. The capacitor includes a plurality of first external terminal electrodes connected to first internal electrodes via a plurality of first feedthrough conductors and a plurality of second external terminal electrodes connected to second internal electrodes via a plurality of second feedthrough conductors. The first external terminal electrodes provided on a first major surface of a capacitor body are connected to via-hole conductors at the hot side for the power source within a substrate, and the second external terminal electrodes provided on first and second major surfaces are connected to grounding via-hole conductors and a mother board within the substrate.

Abstract: A multi-layer capacitor includes first and second side-surface terminal electrodes alternately arranged on four side surfaces of a capacitor body. First and second major-surface terminal electrodes are arranged on a major surface of the capacitor body. First and second internal electrodes which are opposed to each other within the capacitor body are respectively electrically connected at ends thereof to the first and second side-surface terminal electrodes, and are also respectively electrically connected to the first and second major-surface terminal electrodes through via hole conductors. With this arrangement, the directions of the currents flowing within the multi-layer capacitor are diversified, and the lengths of current-carrying paths are shortened so as to achieve a very low ESL value.

Abstract: A multilayer capacitor is constructed to minimize equivalent series inductance (ESL) and to achieve large capacitance. The capacitor includes first and second main go surface terminal electrodes provided on a first main surface of the main body of the multilayer capacitor. First and second side surface terminal electrodes are disposed on four side surfaces of the main body. The main body is divided into a low ESL section of the first main-surface side and a high capacitance section of the second main-surface side. In the low ESL section, in addition to first and second low ESL internal electrodes, a first conductive via-hole electrically connecting the first low ESL internal electrode to the first main surface terminal electrode and a second conductive via-hole electrically connecting the second low ESL internal electrode to the second main surface terminal electrode are provided.