Abstract: A semiconductor wafer includes a base wafer, a sacrificial layer that is lattice-matched or pseudo lattice-matched to the base wafer, a first crystal layer that is formed on the sacrificial layer and made of an epitaxial crystal of SixGe1-x, (0?x<1), and a second crystal layer that is formed on the first crystal layer and made of an epitaxial crystal of a group 3-5 compound semiconductor having a larger band gap than the first crystal layer. The base wafer is, for example, made of single-crystal GaAs. The sacrificial layer is, for example, made of an epitaxial crystal of InmAlnGa1-m-nAs (0?m<1, 0<n?1, 0<n+m?1).

Abstract: To improve the flatness of the surface and improve the reliability of a semiconductor device when expitaxially growing semiconductor crystal layers of different types on a single silicon wafer, provided is a semiconductor wafer which includes: a base wafer having a silicon crystal in the surface thereof, the silicon crystal having a first dent and a second dent; a first Group IVB semiconductor crystal located in the first dent and exposed; a second Group IVB semiconductor crystal located in the second dent; and a Group III-V compound semiconductor crystal located above the second Group IVB semiconductor crystal in the second dent and exposed.

Abstract: Provided is a field-effect transistor including a gate insulating layer, a first semiconductor crystal layer in contact with the gate insulating layer, and a second semiconductor crystal layer lattice-matching or pseudo lattice-matching the first semiconductor crystal layer. Here, the gate insulating layer, the first semiconductor crystal layer, and the second semiconductor crystal layer are arranged in the order of the gate insulating layer, the first semiconductor crystal layer, and the second semiconductor crystal layer, the first semiconductor crystal layer is made of Inx1Ga1-x1Asy1P1-y1 (0<x1?1, 0?y1?1), the second semiconductor crystal layer is made of Inx2Ga1-x2Asy2P1-y2 (0?x2?1, 0?y2?1, y2?y1), and the electron affinity Ea1 of the first semiconductor crystal layer is lower than the electron affinity Ea2 of the second semiconductor crystal layer.

Abstract: A semiconductor substrate includes a substrate, an insulating layer, and a semiconductor layer. The insulating layer is over and in contact with the substrate. The insulating layer includes at least one of an amorphous metal oxide and an amorphous metal nitride. The semiconductor layer is over and in contact with the insulating layer. The semiconductor layer is formed by crystal growth.

Abstract: A sensor includes: a base wafer containing silicon; a seed member provided directly or indirectly on the base wafer; and a photothermal absorber that is made of a Group 3-5 compound semiconductor lattice-matching or pseudo lattice-matching the seed member and being capable of generating a carrier upon absorbing light or heat, where the photothermal absorber outputs an electric signal in response to incident light to be introduced into the photothermal absorber or heat to be applied to the photothermal absorber. A semiconductor wafer includes: a base wafer containing silicon; a seed member provided directly or indirectly on the base wafer; and a photothermal absorber that is made of a Group 3-5 compound semiconductor lattice-matching or pseudo lattice-matching the seed member and being capable of generating a carrier upon absorbing light or heat.

Abstract: The present invention provides a method for producing polycrystalline silicon. The method for producing polycrystalline silicon comprises the steps of (A), (B), and (C), (A) reducing a chlorosilane represented by the formula (1) with a metal at a temperature T1 to obtain a silicon compound; SiHnCl4-n??(1) ?wherein n is an integer of 0 to 3, (B) transferring the silicon compound to a zone having a temperature T2, wherein T1>T2; and (C) depositing polycrystalline silicon in the zone having a temperature T2, wherein the temperature T1 is not less than 1.29 times of a melting point (Kelvin unit) of the metal, and the temperature T2 is higher than a sublimation point or boiling point of the chloride of the metal.

Abstract: A compound semiconductor epitaxial substrate and a process for producing the same are provided. The compound semiconductor epitaxial substrate comprises a single crystal substrate, a lattice mismatch compound semiconductor layer and a stress compensation layer, wherein the lattice mismatch compound semiconductor layer and the stress compensation layer are disposed on the identical surface side of the single crystal substrate, there is no occurrence of lattice relaxation in the lattice mismatch compound semiconductor layer, as well as the stress compensation layer, and Ls representing the lattice constant of the single crystal substrate, Lm representing the lattice constant of the lattice mismatch compound semiconductor layer, and Lc representing the lattice constant of the stress compensation layer satisfy the formula (1a) or (1b).

Abstract: There is provided a light emitting device that includes a base wafer that contains silicon, a plurality of seed bodies provided in contact with the base wafer, and a plurality of Group 3-5 compound semiconductors that are each lattice-matched or pseudo-lattice-matched to corresponding seed bodies. In the device, a light emitting element that emits light in response to current supplied thereto is formed in at least one of the plurality of the Group 3-5 compound semiconductors, and a current limiting element that limits the current supplied to the light emitting element is formed in at least one of the plurality of the Group 3-5 compound semiconductors other than the Group 3-5 compound semiconductor in which the light emitting element is formed.

Abstract: An electric device includes a plurality of circuits that operate in synchronization with a clock signal, a plurality of flip-flops each of which acquires a data value of a signal from a corresponding one of the plurality of circuits in synchronization with the clock signal and stores the acquired data value therein until receiving a next clock signal, where each flip-flop enters into a clock-disabled state, when receiving a signal at a disable terminal thereof, in which the acquired data value continues to be stored in the flip-flop, a timing controller that outputs a hold signal to the disable terminal of each flip-flop at a timing at which a corresponding circuit is desired to be diagnosed, and a plurality of diagnosis lines that are respectively provided in correspondence with the plurality of flip-flops, each diagnosis line outputting as diagnosis data a data value stored in a corresponding flip-flop.

Abstract: Provided is a semiconductor wafer including: a base wafer containing silicon; an inhibitor that has been formed on the base wafer, has an aperture in which a surface of the base wafer is exposed, and inhibits crystal growth; and a light-absorptive structure that has been formed inside the aperture in contact with a surface of the base wafer exposed inside the aperture, where the light-absorptive structure includes a first semiconductor and a second semiconductor.

Abstract: Provided is an optical device including a base wafer containing silicon, a plurality of seed crystals disposed on the base wafer, and a plurality of Group 3-5 compound semiconductors lattice-matching or pseudo lattice-matching the plurality of seed crystals. At least one of the Group 3-5 compound semiconductors has a photoelectric semiconductor formed therein, the photoelectric semiconductor including a light emitting semiconductor that emits light in response to a driving current supplied thereto or a light receiving semiconductor that generates a photocurrent in response to light applied thereto, and at least one of the plurality of Group 3-5 compound semiconductors other than the Group 3-5 compound semiconductor having the photoelectric semiconductor has a heterojunction transistor formed therein.

Abstract: There is provided a semiconductor wafer including a base wafer that has an impurity region in which an impurity atom has been introduced into silicon, a plurality of seed bodies provided in contact with the impurity region, and a plurality of compound semiconductors each provided in contact with the corresponding seed bodies and lattice-matched or pseudo-lattice-matched to the corresponding seed bodies. The semiconductor wafer can further include an inhibitor provided on the base wafer and in which a plurality of apertures exposing at least a part of the impurity region are provided.

Abstract: There is provided a method of measuring a leakage current or a dielectric breakdown voltage of a semiconductor wafer that has a base wafer and a buffer layer formed on the base wafer. The method includes providing, on the buffer layer, a plurality of electrodes including a hole injection electrode made of a material that injects a hole into the buffer layer when an electric field is applied thereto, measuring an electric current flowing through a pair of electrodes or a voltage between the electrodes when a voltage or an electric current is applied to the pair of electrodes, the electrodes including at least one hole injection electrode, and measuring a leakage current or a dielectric breakdown voltage caused by hole migration in the semiconductor wafer based on the current flowing through the pair of electrodes or the voltage generated between the pair of the electrodes.

Abstract: The semiconductor wafer includes: a base wafer; and an inhibition layer that is disposed on the base wafer as one piece or to be separate portions from each other, and inhibits growth of a crystal of a compound semiconductor, where the inhibition layer has a plurality of first opening regions that have a plurality of openings penetrating the inhibition layer and leading to the base wafer, each of the plurality of first opening regions includes therein a plurality of first openings disposed in the same arrangement, some of the plurality of first openings are first element forming openings each provided with a first compound semiconductor on which an electronic element is to be formed, and the other of the plurality of first openings are first dummy openings in which no electronic element is to be formed.

Abstract: There is provided a semiconductor wafer including a base wafer, an insulating layer, and a Si crystal layer in the stated order. The semiconductor wafer further includes an inhibition layer that is provided on the Si crystal layer and has an opening penetrating therethrough to reach the Si crystal layer. The inhibition layer inhibiting crystal growth of a compound semiconductor. Furthermore, a seed crystal is provided within the opening, and a compound semiconductor has a lattice match or a pseudo lattice match with the seed crystal.

Abstract: There is provided a semiconductor device that includes a III-V Group compound semiconductor having a zinc-blende-type crystal structure, an insulating material being in contact with the (111) plane of the III-V Group compound semiconductor, a plane of the III-V Group compound semiconductor equivalent to the (111) plane, or a plane that has an off angle with respect to the (111) plane or the plane equivalent to the (111) plane, and an MIS-type electrode being in contact with the insulating material and including a metal conductive material.

Abstract: A compound semiconductor epitaxial substrate having a pseudomorphic high electron mobility field effect transistor structure including an InGaAs layer as a strained channel layer and an AlGaAs layer containing n type impurities as a front side electron-donating layer, wherein said substrate contains an InGaP layer in an orderly state on the front side of the above described InGaAs layer as the strained channel layer.

Abstract: A semiconductor wafer including: a base wafer; a seed crystal disposed on the base wafer; a compound semiconductor disposed above the seed crystal; and a high resistance layer disposed between the seed crystal and the compound semiconductor, the high resistance layer having a larger resistivity than the seed crystal, and the seed crystal lattice matching or pseudo lattice matching the compound semiconductor is provided.

Abstract: There is provided a method of producing a semiconductor wafer by thermally processing a base wafer having a portion to be thermally processed that has a single-crystal layer and is to be subjected to thermal processing and a portion to be protected that is to be protected from heal, to be added during the thermal processing. The method comprises a step of forming, above the portion to be protected, a protective layer for protecting the portion to be protected from an electromagnetic wave to be applied to the base wafer, and a step of annealing the portion to be thermally processed, by applying the electromagnetic wave to the entire base wafer.

Abstract: There is provided a method of producing a semiconductor wafer by thermally processing a base water having a portion to be thermally processed that is to be thermally processed. The method comprises a step of providing, on the base wafer, a portion to be heated that generates heat through absorption of an electromagnetic wave and selectively heats the portion to be thermally processed, a step of applying an electromagnetic wave to the base wafer, and a step of lowering the lattice defect density of the portion to he thermally processed, by means of the heat generated by the portion to be heated through the absorption of the electromagnetic wave.