Abstract: An electric device includes a plurality of circuits that operate in synchronization with a clock signal, a plurality of flip-flops each of which acquires a data value of a signal from a corresponding one of the plurality of circuits in synchronization with the clock signal and stores the acquired data value therein until receiving a next clock signal, where each flip-flop enters into a clock-disabled state, when receiving a signal at a disable terminal thereof, in which the acquired data value continues to be stored in the flip-flop, a timing controller that outputs a hold signal to the disable terminal of each flip-flop at a timing at which a corresponding circuit is desired to be diagnosed, and a plurality of diagnosis lines that are respectively provided in correspondence with the plurality of flip-flops, each diagnosis line outputting as diagnosis data a data value stored in a corresponding flip-flop.

Abstract: The present invention provides a gallium nitride type epitaxial crystal, a method for producing the crystal, and a field effect transistor using the crystal. The gallium nitride type epitaxial crystal comprises a base substrate and the following (a) to (e), wherein a connection layer comprising a gallium nitride type crystal is arranged in an opening of the non-gallium nitride type insulating layer to electrically connect the first buffer layer and the p-conductive type semiconductor crystal layer. (a) a gate layer, (b) a high purity first buffer layer containing a channel layer contacting an interface on the base substrate side of the gate layer, (c) a second buffer layer arranged on the base substrate side of the first buffer layer, (d) a non-gallium nitride type insulating layer arranged on the base substrate side of the second buffer layer, and having the opening at a part thereof, and (e) a p-conductive type semiconductor crystal layer arranged on the base substrate side of the insulating layer.

Abstract: The present invention provides a method for manufacturing a gallium nitride semiconductor epitaxial crystal substrate with a dielectric film which has a low gate leak current and negligibly low gate lag, drain lag, and current collapse characteristics. The method for manufacturing a semiconductor epitaxial crystal substrate is a method for manufacturing a semiconductor epitaxial crystal substrate in which a dielectric layer of a nitride dielectric material or an oxide dielectric material in an amorphous form functioning as a passivation film or a gate insulator is provided on a surface of a nitride semiconductor crystal layer grown by metal organic chemical vapor deposition. In the method, after the nitride semiconductor crystal layer is grown in an epitaxial growth chamber, the dielectric layer is grown on the nitride semiconductor crystal layer in the epitaxial growth chamber.

Abstract: The present invention provides an epitaxial substrate for field effect transistor. In the epitaxial substrate for field effect transistor, a nitride-based Group III-V semiconductor epitaxial crystal containing Ga is interposed between the ground layer and the operating layer, and the nitride-based Group III-V semiconductor epitaxial crystal comprises the following (i), (ii) and (iii). (i) a first buffer layer containing Ga or Al and containing a high resistivity crystal layer having added thereto compensation impurity element present in the same period as Ga in the periodic table and having small atomic number; (ii) a second buffer layer containing Ga or Al, laminated on the operating layer side of the first buffer layer; and (iii) a high purity epitaxial crystal layer containing acceptor impurities in a slight amount such that non-addition or depletion state can be maintained, provided between the high resistivity layer and the operating layer.

Abstract: The present invention provides a method for producing a Group III-V compound semiconductor, comprising a step of feeding a Group III raw material, a Group V raw material, a carrier gas, and if necessary, other raw materials, to a reactor to grow a Group III-V compound semiconductor on a substrate in the reactor by a metalorganic vapor phase epitaxy, wherein the Group III raw material and the Group V raw material are independently fed to the reactor, and hydrogen halide is fed to the reactor together with a raw material other than the Group V raw material, or the carrier gas.

Abstract: A compound semiconductor substrate manufacturing method suitable for manufacturing a compound semiconductor element having high electrical characteristics. The compound semiconductor substrate manufacturing method is a method for manufacturing a compound semiconductor substrate having pn junction, including an epitaxial growing process, a selective growing process and other discretionary processes after the epitaxial growing process. The highest temperatures in the selective growing process and other discretionary processes after the epitaxial growing process are lower than that in the epitaxial growing process prior to the selective growing process.

Abstract: A monolithic light-emitting device and driving method therefore includes a plurality of light-emitting diodes, array-arranged monolithically on a single substrate. Thie light-emitting diodes include a pn junction-containing semiconductor material and a phosphor-containing layer passing light emitted from the semiconductor material, absorbing part, or whole of the light for conversion into light having a different wavelength. The array is constituted of a light-emitting diode group consisting of m (m?2) pieces of the light-emitting diode, the light emitting diode group being constituted of N types (N?2, providing N?m) of light-emitting diodes, each having either one of preset N types of light-emitting spectrum patterns. An average light-emitting spectrum from the whole array can be changed by regulating a power supplied to the light-emitting diodes for each light-emitting diode group sorted according to the type of the light-emitting spectrum pattern.

Abstract: The present invention provides a method for producing polycrystalline silicon. The method for producing polycrystalline silicon comprises the steps of (A), (B), and (C), (A) reducing a chlorosilane represented by the formula (1) with a metal at a temperature Ti to obtain a silicon compound; SiHnCl4-n??(1) wherein n is an integer of 0 to 3, (B) transferring the silicon compound to a zone having a temperature T2, wherein T1>T2; and (C) depositing polycrystalline silicon in the zone having a temperature T2, wherein the temperature T1 is not less than 1.29 times of a melting point (Kelvin unit) of the metal, and the temperature T2 is higher than a sublimation point or boiling point of the chloride of the metal.

Abstract: There is provided a clock transferring apparatus that outputs input data given in synchronization with a transmission clock in synchronization with an internal clock having a phase different from that of the transmission clock. The clock transferring apparatus includes: a comparison clock generating section that generates a comparison clock of which each clock rising edge or each clock falling edge coincides with substantially middle position on an open part of eye of the corresponding input data based on the transmission clock; an initializing section that controls a phase of the internal clock so that the phase of the internal clock is the substantially same as a phase of the comparison clock; and a data outputting section that receives the internal clock of which the phase is controlled by the initializing section and the input data, synchronizes the input data with the internal clock, and outputs the synchronized data as output data.

Abstract: Disclosed is a method for producing a compound semiconductor epitaxial substrate having a pn junction by selective growth which is characterized by using a base substrate having an average residual strain of not more than 1.0×10?5.

Abstract: Provided is a test apparatus including: test signal supply sections supplying a test signal writing test data to the connected memory under test, to a terminal of the memory; terminal correspondence determination sections outputting a terminal unit determination result indicating whether test data from the connected terminal matches an expected value; a determination result selection section selecting, for each memory, terminal unit determination results from the terminal correspondence determination sections; a memory correspondence determination section determining whether writing succeeded to each memory, based on the selection result by the determination result selection section; an identifying section identifying a test signal supply section connected to the memory to which writing succeeded and a test signal supply section connected to the memory to which writing failed; and a mask treatment section instructing each test signal supply section whether to perform re-testing, according to whether writing s

Abstract: A compound semiconductor substrate manufacturing method suitable for manufacturing a compound semiconductor element having high electrical characteristics. The compound semiconductor substrate manufacturing method is a method for manufacturing a compound semiconductor substrate having pn junction, including an epitaxial growing process, a selective growing process and other discretionary processes after the epitaxial growing process. The highest temperatures in the selective growing process and other discretionary processes after the epitaxial growing process are lower than that in the epitaxial growing process prior to the selective growing process.

Abstract: A compound semiconductor epitaxial substrate and a process for producing the same are provided. The compound semiconductor epitaxial substrate comprises a single crystal substrate, a lattice mismatch compound semiconductor layer and a stress compensation layer, wherein the lattice mismatch compound semiconductor layer and the stress compensation layer are disposed on the identical surface side of the single crystal substrate, there is no occurrence of lattice relaxation in the lattice mismatch compound semiconductor layer, as well as the stress compensation layer, and Ls representing the lattice constant of the single crystal substrate, Lm representing the lattice constant of the lattice mismatch compound semiconductor layer, and Lc representing the lattice constant of the stress compensation layer satisfy the formula (1a) or (1b).

Abstract: An InGaP buffer layer (3) is formed on a semi-insulating GaAs substrate (1) to a thickness of not less than 5 nm and not greater than 500 nm and an InAlAs layer (4) and an InGaAs channel layer (5) are grown thereon to form a heterostructure. An In segregation effect occurs at the time of forming the InGaP buffer layer (3), so that the region of the InGaP buffer layer (3) near the layer above becomes excessive in In. As a result, the composition of the surface of the InGaP buffer layer (3) becomes very close to the composition of InP, thereby suppressing occurrence of misfit dislocations that can result in degradation of the surface condition. Further, the surface condition of the InAlAs layer (4) and InGaAs channel layer (5) formed thereon can be made good.

Abstract: The present invention provides a method for manufacturing a compound semiconductor substrate. The method for manufacturing a compound semiconductor substrate comprises the steps of: (a) epitaxially growing a compound semiconductor functional layer 2 on a substrate 1, (b) bonding a support substrate 3 to the compound semiconductor functional layer 2, (c) polishing the substrate 1 and a part of the compound semiconductor functional layer 2 on the side which is in contact with the substrate 1, to remove them, (d) bonding a thermally conductive substrate 4 having a thermal conductivity higher than that of the substrate 1 to the exposed surface of the compound semiconductor functional layer 2 which is provided in the step (c) to obtain a multilayer substrate and (d) separating the support substrate 3 from the multilayer substrate.

Abstract: In an epitaxial substrate comprising a bipolar transistor structure having a collector layer (3), base layer (4) and emitter layer (5) on a GaAs substrate (2), the base layer (4) is configured a lower base layer (41) having a required carrier concentration, an upper base layer (42), and a low carrier concentration layer (43) provided between the lower base layer (41) and the upper base layer (42) that has a ballast effect. The lower base layer (41) or the upper base layer (42) may be omitted. The higher the temperature of the low carrier concentration layer (43) portion is, the easier it is for electrons to pass therethrough, which has the effect of raising the amplification factor, thereby helping the transistor heat stability characteristics.

Abstract: A compound semiconductor epitaxial substrate having a pseudomorphic high electron mobility field effect transistor structure including an InGaAs layer as a strained channel layer and an AlGaAs layer containing n type impurities as a front side electron-donating layer, wherein said substrate contains an InGaP layer in an orderly state on the front side of the above described InGaAs layer as the strained channel layer.

Abstract: In an epitaxial substrate (20) comprising a collector layer (22), a base layer (23) and an emitter layer (24) formed on a semi-insulating GaAs substrate (21), a hole barrier layer (22C) is provided in the collector layer (22) to prevent influx of holes from the base layer (23), whereby the flow of collector current is suppressed when the collector current density rises and electron velocity is saturated, suppressing thermal runaway of the collector current without a ballast resistance or the like. Also, thermal runaway of the collector current is suppressed by providing an additional layer (2C) for generating, in the conduction band, an electron barrier by means of electrons accumulated in the collector layer (2) when the collector current density rises.

Abstract: There is provided a clock transferring apparatus that outputs input data given in synchronization with a transmission clock in synchronization with an internal clock having a phase different from that of the transmission clock. The clock transferring apparatus includes: a comparison clock generating section that generates a comparison clock of which each clock rising edge or each clock falling edge coincides with substantially middle position on an open part of eye of the corresponding input data based on the transmission clock; an initializing section that controls a phase of the internal clock so that the phase of the internal clock is the substantially same as a phase of the comparison clock; and a data outputting section that receives the internal clock of which the phase is controlled by the initializing section and the input data, synchronizes the input data with the internal clock, and outputs the synchronized data as output data.

Abstract: The n+-GaAs layer 8 of the GaAs single crystal 10 is formed by epitaxial growth, followed by epitaxially growing the Si-layer 11 in the same epitaxial growth furnace, and then the aluminum electrode 12 is formed on the Si-layer 11 as an ohmic electrode. The Si-layer 11 can suppress the formation of a surface defect level on the surface of the n+-GaAs layer 8 and can effectively prevent the formation of an unnecessary potential barrier. Since the Si-layer 11 has a smooth surface and is excellent in chemical stability, a good ohmic electrode can be obtained by forming the electrode 12 using aluminum or the like has a suitable work function to the Si-layer 11.