Patents by Inventor Masahiko Hayakawa

Masahiko Hayakawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190067336
    Abstract: It is an object of the present invention to provide a semiconductor display device having an interlayer insulating film which can obtain planarity of a surface while controlling film formation time, can control treatment time of heating treatment with an object of removing moisture, and can prevent moisture in the interlayer insulating film from being discharged to a film or an electrode adjacent to the interlayer insulating film. An inorganic insulating film containing nitrogen, which is less likely to transmit moisture compared with an organic resin, is formed so as to cover a TFT. Next, an organic resin film containing photosensitive acrylic resin is applied to the organic insulting film, and the organic resin film is partially exposed to light to be opened. Thereafter, an inorganic insulting film containing nitrogen, which is less likely to transmit moisture compared with an organic resin, is fanned so as to cover the opened organic resin film.
    Type: Application
    Filed: August 21, 2018
    Publication date: February 28, 2019
    Inventors: Shunpei YAMAZAKI, Satoshi MURAKAMI, Masahiko HAYAKAWA, Kiyoshi KATO, Mitsuaki OSAME
  • Publication number: 20190043896
    Abstract: A display device including a semiconductor element is provided.
    Type: Application
    Filed: August 8, 2018
    Publication date: February 7, 2019
    Inventors: Satoshi MURAKAMI, Masahiko HAYAKAWA, Shunpei YAMAZAKI
  • Publication number: 20190027108
    Abstract: To reduce power consumption of a display device with the use of a simple structure and a simple operation. The display device includes an input device. Input of an image signal to a driver circuit is controlled in accordance with an image operation signal output from the input device. Specifically, input of image signals at the time when the input device is not operated is less frequent than that at the time when the input device is operated. Accordingly, display degradation (deterioration of display quality) caused when the display device is used can be prevented and power consumed when the display device is not used can be reduced.
    Type: Application
    Filed: September 27, 2018
    Publication date: January 24, 2019
    Inventors: Kenichi WAKIMOTO, Masahiko HAYAKAWA
  • Publication number: 20190012119
    Abstract: In an image forming apparatus, a plurality of light emitting portions arrayed in an array direction. A lens array has a length in the array direction longer than a length in a direction orthogonal to the array direction. A controller is configured to perform: converting a reference printing pattern including a plurality of first linear patterns to a detection pattern including a plurality of second linear patterns, each of the plurality of first linear patterns forming a first angle with respect to a reference line parallel to the array direction, each of the plurality of second linear patterns forming a second angle smaller than the first angle with respect to the reference line; forming a detection pattern image on a transfer medium; detecting a print density of the detection pattern image with a sensor; and setting an image formation condition according to the print density detected by the sensor.
    Type: Application
    Filed: July 3, 2018
    Publication date: January 10, 2019
    Inventors: Kensuke Miyahara, Masahiko Hayakawa, Toshio Furukawa, Junichi Yokoi
  • Publication number: 20190006393
    Abstract: A semiconductor device which includes an oxide semiconductor and in which formation of a parasitic channel due to a gate BT stress is suppressed is provided. Further, a semiconductor device including a transistor having excellent electrical characteristics is provided. The semiconductor device includes a transistor having a dual-gate structure in which an oxide semiconductor film is provided between a first gate electrode and a second gate electrode; gate insulating films are provided between the oxide semiconductor film and the first gate electrode and between the oxide semiconductor film and the second gate electrode; and in the channel width direction of the transistor, the first or second gate electrode faces a side surface of the oxide semiconductor film with the gate insulating film between the oxide semiconductor film and the first or second gate electrode.
    Type: Application
    Filed: July 19, 2018
    Publication date: January 3, 2019
    Inventors: Shunpei YAMAZAKI, Hiroyuki MIYAKE, Kenichi OKAZAKI, Masahiko HAYAKAWA, Shinpei MATSUDA
  • Publication number: 20180374957
    Abstract: A semiconductor device including a transistor and a wiring electrically connected to the transistor each of which has excellent electrical characteristics because of specific structures thereover is provided. A first conductive film, a first insulating film over the first conductive film, a second conductive film over the first insulating film, a second insulating film over the second conductive film, a third conductive film electrically connected to the first conductive film through an opening provided in the first insulating film and the second insulating film, and a third insulating film over the third conductive film are provided. The third conductive film includes indium, tin, and oxygen, and the third insulating film includes silicon and nitrogen and the number of ammonia molecules released from the third insulating film is less than or equal to 1×1015 molecules/cm3 by thermal desorption spectroscopy.
    Type: Application
    Filed: August 23, 2018
    Publication date: December 27, 2018
    Inventors: Masahiro KATAYAMA, Yasutaka NAKAZAWA, Masatoshi YOKOYAMA, Masahiko HAYAKAWA, Kenichi OKAZAKI, Shunsuke KOSHIOKA
  • Patent number: 10134766
    Abstract: The number of photolithography steps used for manufacturing a transistor is reduced to less than the conventional one and a highly reliable semiconductor device is provided. The present invention relates to a semiconductor device including a circuit including a transistor having an oxide semiconductor layer over a first substrate and a second substrate fixed to the first substrate with a sealant. A closed space surrounded by the sealant, the first substrate, and the second substrate is in a reduced pressure state or filled with dry air. The sealant surrounds at least the transistor and has a closed pattern shape. Further, the circuit is a driver circuit including a transistor having an oxide semiconductor layer.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: November 20, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masahiko Hayakawa, Yuta Moriya, Junya Goto, Yasuyuki Arai
  • Patent number: 10089946
    Abstract: To reduce power consumption of a display device with the use of a simple structure and a simple operation. The display device includes an input device. Input of an image signal to a driver circuit is controlled in accordance with an image operation signal output from the input device. Specifically, input of image signals at the time when the input device is not operated is less frequent than that at the time when the input device is operated. Accordingly, display degradation (deterioration of display quality) caused when the display device is used can be prevented and power consumed when the display device is not used can be reduced.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: October 2, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kenichi Wakimoto, Masahiko Hayakawa
  • Patent number: 10084096
    Abstract: After a sputtering gas is supplied to a deposition chamber, plasma including an ion of the sputtering gas is generated in the vicinity of a target. The ion of the sputtering gas is accelerated and collides with the target, so that flat-plate particles and atoms of the target are separated from the target. The flat-plate particles are deposited with a gap therebetween so that the flat plane faces a substrate. The atom and the aggregate of the atoms separated from the target enter the gap between the deposited flat-plate particles and grow in the plane direction of the substrate to fill the gap. A film is formed over the substrate. After the deposition, heat treatment is performed at high temperature in an oxygen atmosphere, which forms an oxide with a few oxygen vacancies and high crystallinity.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: September 25, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Haruyuki Baba, Akio Suzuki, Hiromi Sawai, Masahiko Hayakawa, Noritaka Ishihara, Masashi Oota
  • Patent number: 10083995
    Abstract: It is an object of the present invention to provide a semiconductor display device having an interlayer insulating film which can obtain planarity of a surface while controlling film formation time, can control treatment time of heating treatment with an object of removing moisture, and can prevent moisture in the interlayer insulating film from being discharged to a film or an electrode adjacent to the interlayer insulating film. An inorganic insulating film containing nitrogen, which is less likely to transmit moisture compared with an organic resin, is formed so as to cover a TFT. Next, an organic resin film containing photosensitive acrylic resin is applied to the organic insulting film, and the organic resin film is partially exposed to light to be opened. Thereafter, an inorganic insulting film containing nitrogen, which is less likely to transmit moisture compared with an organic resin, is formed so as to cover the opened organic resin film.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: September 25, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Murakami, Masahiko Hayakawa, Kiyoshi Kato, Mitsuaki Osame
  • Patent number: 10062742
    Abstract: Semiconductor elements deteriorate or are destroyed due to electrostatic discharge damage. The present invention provides a semiconductor device in which a protecting means is formed in each pixel. The protecting means is provided with one or a plurality of elements selected from the group consisting of resistor elements, capacitor elements, and rectifying elements. Sudden changes in the electric potential of a source electrode or a drain electrode of a transistor due to electric charge that builds up in a pixel electrode is relieved by disposing the protecting means between the pixel electrode of the light-emitting element and the source electrode or the drain electrode of the transistor. Deterioration or destruction of the semiconductor element due to electrostatic discharge damage is thus prevented.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: August 28, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masahiko Hayakawa, Yoshifumi Tanada, Mitsuaki Osame, Aya Anzai, Ryota Fukumoto
  • Patent number: 10050065
    Abstract: A display device including a semiconductor element is provided.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: August 14, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Murakami, Masahiko Hayakawa, Shunpei Yamazaki
  • Patent number: 10043828
    Abstract: A semiconductor device which includes an oxide semiconductor and in which formation of a parasitic channel due to a gate BT stress is suppressed is provided. Further, a semiconductor device including a transistor having excellent electrical characteristics is provided. The semiconductor device includes a transistor having a dual-gate structure in which an oxide semiconductor film is provided between a first gate electrode and a second gate electrode; gate insulating films are provided between the oxide semiconductor film and the first gate electrode and between the oxide semiconductor film and the second gate electrode; and in the channel width direction of the transistor, the first or second gate electrode faces a side surface of the oxide semiconductor film with the gate insulating film between the oxide semiconductor film and the first or second gate electrode.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: August 7, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hiroyuki Miyake, Kenichi Okazaki, Masahiko Hayakawa, Shinpei Matsuda
  • Publication number: 20180190677
    Abstract: A semiconductor device production system using a laser crystallization method is provided which can avoid forming grain boundaries in a channel formulation region of a TFT, thereby preventing grain boundaries from lowering the mobility of the TFT greatly, from lowering ON current, and from increasing OFF current. Rectangular or stripe pattern depression and projection portions are formed on an insulating film. A semiconductor film is formed on the insulating film. The semiconductor film is irradiated with continuous wave laser light by running the laser light along the stripe pattern depression and projection portions of the insulating film or along the major or minor axis direction of the rectangle. Although continuous wave laser light is most preferred among laser light, it is also possible to use pulse oscillation laser light in irradiating the semiconductor film.
    Type: Application
    Filed: February 15, 2018
    Publication date: July 5, 2018
    Inventors: Atsuo ISOBE, Shunpei YAMAZAKI, Koji DAIRIKI, Hiroshi SHIBATA, Chiho KOKUBO, Tatsuya ARAO, Masahiko HAYAKAWA, Hidekazu MIYAIRI, Akihisa SHIMOMURA, Koichiro TANAKA, Mai AKIBA
  • Publication number: 20180190745
    Abstract: The present invention provides a TFT that has a channel length particularly longer than that of an existing one, specifically, several tens to several hundreds times longer than that of the existing one, and thereby allowing turning to an on-state at a gate voltage particularly higher than the existing one and driving, and allowing having a low channel conductance gd. According to the present invention, not only the simple dispersion of on-current but also the normalized dispersion thereof can be reduced, and other than the reduction of the dispersion between the individual TFTs, the dispersion of the OLEDs themselves and the dispersion due to the deterioration of the OLED can be reduced.
    Type: Application
    Filed: February 13, 2018
    Publication date: July 5, 2018
    Inventors: Makoto Udagawa, Masahiko Hayakawa, Jun Koyama, Mitsuaki Osame, Aya Anzai
  • Publication number: 20180122884
    Abstract: Semiconductor elements deteriorate or are destroyed due to electrostatic discharge damage. The present invention provides a semiconductor device in which a protecting means is formed in each pixel. The protecting means is provided with one or a plurality of elements selected from the group consisting of resistor elements, capacitor elements, and rectifying elements. Sudden changes in the electric potential of a source electrode or a drain electrode of a transistor due to electric charge that builds up in a pixel electrode is relieved by disposing the protecting means between the pixel electrode of the light-emitting element and the source electrode or the drain electrode of the transistor. Deterioration or destruction of the semiconductor element due to electrostatic discharge damage is thus prevented.
    Type: Application
    Filed: December 18, 2017
    Publication date: May 3, 2018
    Inventors: Shunpei YAMAZAKI, Masahiko HAYAKAWA, Yoshifumi TANADA, Mitsuaki OSAME, Aya ANZAI, Ryota FUKUMOTO
  • Patent number: 9939692
    Abstract: The following semiconductor device provides high reliability and a narrower frame width. The semiconductor device includes a driver circuit and a pixel portion. The driver circuit has a first transistor including a first gate and a second gate electrically connected to each other with a semiconductor film sandwiched therebetween, and a second transistor electrically connected to the first transistor. The pixel portion includes a third transistor, a liquid crystal element, and a capacitor. The liquid crystal element includes a first transparent conductive film electrically connected to the third transistor, a second conductive film, and a liquid crystal layer. The capacitor includes the first conductive film, a third transparent conductive film, and a nitride insulating film. The nitride insulating film is positioned between the first transparent conductive film and the third transparent conductive film, and positioned between the semiconductor film and the second gate of the first transistor.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: April 10, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hiroyuki Miyake, Kouhei Toyotaka, Masahiko Hayakawa, Daisuke Matsubayashi, Shinpei Matsuda
  • Publication number: 20180059579
    Abstract: A developing device includes a developer cartridge and a developing unit. The developer cartridge, in some instances, may include a shutter. This shutter may have a wall for closing a developer supply hole, and be movable, with respect to a developer cartridge casing, between an open position where the supply hole is opened by the wall and a closed position where the supply hole is closed by the wall. The shutter may further include a protrusion that is movable with respect to the wall of the shutter between a first position and a second position in an axial direction. The protrusion, in the first position, is engageable with a developing unit and, in the second position, would be disengaged from the developing unit.
    Type: Application
    Filed: November 7, 2017
    Publication date: March 1, 2018
    Inventors: Masahiko Hayakawa, Masashi Imai, Shougo Sato
  • Patent number: 9905702
    Abstract: Provided is a bottom-gate transistor including an oxide semiconductor, in which electric-field concentration which might occur in the vicinity of an end portion of a drain electrode layer (and the vicinity of an end portion of a source electrode layer) when a high gate voltage is applied to a gate electrode layer is reduced and degradation of switching characteristics is suppressed, so that the reliability is improved. The cross-sectional shape of an insulating layer which overlaps over a channel formation region is a tapered shape. The thickness of the insulating layer which overlaps over the channel formation region is 0.3 ?m or less, preferably 5 nm or more and 0.1 ?m or less. The taper angle ? of a lower end portion of the cross-sectional shape of the insulating layer which overlaps over the channel formation region is 60° or smaller, preferably 45° or smaller, further preferably 30° or smaller.
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: February 27, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masahiko Hayakawa, Satoshi Shinohara
  • Patent number: 9905624
    Abstract: The present invention provides a TFT that has a channel length particularly longer than that of an existing one, specifically, several tens to several hundreds times longer than that of the existing one, and thereby allowing turning to an on-state at a gate voltage particularly higher than the existing one and driving, and allowing having a low channel conductance gd. According to the present invention, not only the simple dispersion of on-current but also the normalized dispersion thereof can be reduced, and other than the reduction of the dispersion between the individual TFTs, the dispersion of the OLEDs themselves and the dispersion due to the deterioration of the OLED can be reduced.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: February 27, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Makoto Udagawa, Masahiko Hayakawa, Jun Koyama, Mitsuaki Osame, Aya Anzai