Patents by Inventor Masahiko Hayakawa

Masahiko Hayakawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9899419
    Abstract: A semiconductor device production system using a laser crystallization method is provided which can avoid forming grain boundaries in a channel formation region of a TFT, thereby preventing grain boundaries from lowering the mobility of the TFT greatly, from lowering ON current, and from increasing OFF current. Rectangular or stripe pattern depression and projection portions are formed on an insulating film. A semiconductor film is formed on the insulating film. The semiconductor film is irradiated with continuous wave laser light by running the laser light along the stripe pattern depression and projection portions of the insulating film or along the major or minor axis direction of the rectangle. Although continuous wave laser light is most preferred among laser light, it is also possible to use pulse oscillation laser light in irradiating the semiconductor film.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: February 20, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Atsuo Isobe, Shunpei Yamazaki, Koji Dairiki, Hiroshi Shibata, Chiho Kokubo, Tatsuya Arao, Masahiko Hayakawa, Hidekazu Miyairi, Akihisa Shimomura, Koichiro Tanaka, Mai Akiba
  • Patent number: 9899420
    Abstract: In a pixel including a selection transistor, a driver transistor, and a light-emitting element, as the driver transistor, a transistor is used in which a channel is formed in an oxide semiconductor film and its channel length is 0.5 ?m or greater and 4.5 ?m or less. The driver transistor includes a first gate electrode over an oxide semiconductor film and a second gate electrode below the oxide semiconductor film. The first gate electrode and the second gate electrode are electrically connected to each other and overlap with the oxide semiconductor film. Furthermore, in the selection transistor of a pixel, which does not need to have field-effect mobility as high as that of the driver transistor, a channel length is made longer than at least the channel length of the driver transistor.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: February 20, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hiroyuki Miyake, Seiko Inoue, Shinpei Matsuda, Daisuke Matsubayashi, Masahiko Hayakawa
  • Publication number: 20180026153
    Abstract: A-light-emitting device which realizes a high aperture ratio and in which the quality of image is little affected by the variation in the characteristics of TFTs. The channel length of the driving TFTs is selected to be very larger than the channel width of the driving TFTs to improve current characteristics in the saturated region, and a high VGS is applied to the driving TFTs to obtain a desired drain current. Therefore, the drain currents of the driving TFTs are little affected by the variation in the threshold voltage. In laying out the pixels, further, wiring is arranged under the partitioning wall and the driving This are arranged under the wiring in order to avoid a decrease in the aperture ratio despite of an increase in the size of the driving TFT.
    Type: Application
    Filed: August 9, 2017
    Publication date: January 25, 2018
    Inventors: Mitsuaki OSAME, Aya ANZAI, Jun KOYAMA, Makoto UDAGAWA, Masahiko HAYAKAWA, Shunpei YAMAZAKI
  • Patent number: 9876118
    Abstract: Provided is a semiconductor device including a transistor having excellent electrical characteristics (e.g., on-state current, field-effect mobility, or frequency characteristics) or a semiconductor device including a transistor with high reliability. In the channel width direction of a channel-etched transistor in which an oxide semiconductor film is between first and second gate electrodes, the first and second gate electrodes are connected to each other through an opening portion in first and second gate insulating films. In addition, the first and second gate electrodes surround the oxide semiconductor film in a cross-section in the channel width direction, with the first gate insulating film provided between the first gate electrode and the oxide semiconductor film and the second gate insulating film provided between the second gate electrode and the oxide semiconductor film. Furthermore, the channel length of the transistor is 0.5 ?m or longer and 6.5 ?m or shorter.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: January 23, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masahiko Hayakawa, Shinpei Matsuda, Daisuke Matsubayashi
  • Publication number: 20180013005
    Abstract: After a sputtering gas is supplied to a deposition chamber, plasma including an ion of the sputtering gas is generated in the vicinity of a target. The ion of the sputtering gas is accelerated and collides with the target, so that flat-plate particles and atoms of the target are separated from the target. The flat-plate particles are deposited with a gap therebetween so that the flat plane faces a substrate. The atom and the aggregate of the atoms separated from the target enter the gap between the deposited flat-plate particles and grow in the plane direction of the substrate to fill the gap. A film is formed over the substrate. After the deposition, heat treatment is performed at high temperature in an oxygen atmosphere, which forms an oxide with a few oxygen vacancies and high crystallinity.
    Type: Application
    Filed: September 7, 2017
    Publication date: January 11, 2018
    Inventors: Shunpei YAMAZAKI, Haruyuki BABA, Akio SUZUKI, Hiromi SAWAI, Masahiko HAYAKAWA, Noritaka ISHIHARA, Masashi OOTA
  • Patent number: 9859353
    Abstract: Semiconductor elements deteriorate or are destroyed due to electrostatic discharge damage. The present invention provides a semiconductor device in which a protecting means is formed in each pixel. The protecting means is provided with one or a plurality of elements selected from the group consisting of resistor elements, capacitor elements, and rectifying elements. Sudden changes in the electric potential of a source electrode or a drain electrode of a transistor due to electric charge that builds up in a pixel electrode is relieved by disposing the protecting means between the pixel electrode of the light-emitting element and the source electrode or the drain electrode of the transistor. Deterioration or destruction of the semiconductor element due to electrostatic discharge damage is thus prevented.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: January 2, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masahiko Hayakawa, Yoshifumi Tanada, Mitsuaki Osame, Aya Anzai, Ryota Fukumoto
  • Patent number: 9823602
    Abstract: A developing device includes a developer cartridge and a developing unit. The developer cartridge, in some instances, may include a shutter. This shutter may have a wall for closing a developer supply hole, and be movable, with respect to a developer cartridge casing, between an open position where the supply hole is opened by the wall and a closed position where the supply hole is closed by the wall. The shutter may further include a protrusion that is movable with respect to the wall of the shutter between a first position and a second position in an axial direction. The protrusion, in the first position, is engageable with a developing unit and, in the second position, would be disengaged from the developing unit.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: November 21, 2017
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventors: Masahiko Hayakawa, Masashi Imai, Shougo Sato
  • Publication number: 20170315644
    Abstract: A display device is provided. An input/output device is provided. A data processing device is provided. A display method is provided. The display device includes a display panel and a control portion. The control portion has a function of receiving image data and control data, a function of generating first data on the basis of the image data, a function of generating second data on the basis of the image data, a function of detecting a contour portion from the image data, a function of generating third data in which the contour portion is emphasized, and a function of supplying the first to third data. The display panel has a function of receiving the first to third data and includes a pixel. The pixel includes a first display element and a second display element. The first display element has a function of displaying an image on the basis of the first data, and the second display element has a function of displaying an image on the basis of the second or third data.
    Type: Application
    Filed: April 19, 2017
    Publication date: November 2, 2017
    Inventor: Masahiko HAYAKAWA
  • Patent number: 9806096
    Abstract: An object of the present invention is to prevent the deterioration of a TFT (thin film transistor). The deterioration of the TFT by a BT test is prevented by forming a silicon oxide nitride film between the semiconductor layer of the TFT and a substrate, wherein the silicon oxide nitride film ranges from 0.3 to 1.6 in a ratio of the concentration of N to the concentration of Si.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: October 31, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masahiko Hayakawa, Mitsunori Sakama, Satoshi Toriumi
  • Publication number: 20170309650
    Abstract: A semiconductor device which includes an oxide semiconductor and in which formation of a parasitic channel due to a gate BT stress is suppressed is provided. Further, a semiconductor device including a transistor having excellent electrical characteristics is provided. The semiconductor device includes a transistor having a dual-gate structure in which an oxide semiconductor film is provided between a first gate electrode and a second gate electrode; gate insulating films are provided between the oxide semiconductor film and the first gate electrode and between the oxide semiconductor film and the second gate electrode; and in the channel width direction of the transistor, the first or second gate electrode faces a side surface of the oxide semiconductor film with the gate insulating film between the oxide semiconductor film and the first or second gate electrode.
    Type: Application
    Filed: July 10, 2017
    Publication date: October 26, 2017
    Inventors: Shunpei YAMAZAKI, Hiroyuki MIYAKE, Kenichi OKAZAKI, Masahiko HAYAKAWA, Shinpei MATSUDA
  • Patent number: 9799298
    Abstract: A display device in which power consumed in an image holding period is suppressed. The display device includes a liquid crystal display panel which is driven by power supplied from a converter or a backup circuit. A fixed potential may be supplied and a capacitor may be charged with the use of the converter in a writing operation where a load is large, and the fixed potential may be preferentially supplied from the capacitor without using the converter in an image holding period when the load is small.
    Type: Grant
    Filed: April 22, 2011
    Date of Patent: October 24, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masahiko Hayakawa, Shinya Okano
  • Patent number: 9768207
    Abstract: It is an object to provide a manufacturing method of a structure of a thin film transistor including an oxide semiconductor film, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible. A protective insulating layer is formed to cover a thin film transistor including an oxide semiconductor layer that is dehydrated or dehydrogenated by first heat treatment, and second heat treatment at a temperature that is lower than that of the first heat treatment, in which the increase and decrease in temperature are repeated plural times, is performed, whereby a thin film transistor including an oxide semiconductor layer, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible without depending on the channel length, can be manufactured.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: September 19, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masashi Tsubuku, Shuhei Yoshitomi, Takahiro Tsuji, Miyuki Hosoba, Junichiro Sakata, Hiroyuki Tomatsu, Masahiko Hayakawa
  • Patent number: 9761733
    Abstract: After a sputtering gas is supplied to a deposition chamber, plasma including an ion of the sputtering gas is generated in the vicinity of a target. The ion of the sputtering gas is accelerated and collides with the target, so that flat-plate particles and atoms of the target are separated from the target. The flat-plate particles are deposited with a gap therebetween so that the flat plane faces a substrate. The atom and the aggregate of the atoms separated from the target enter the gap between the deposited flat-plate particles and grow in the plane direction of the substrate to fill the gap. A film is formed over the substrate. After the deposition, heat treatment is performed at high temperature in an oxygen atmosphere, which forms an oxide with a few oxygen vacancies and high crystallinity.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: September 12, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Haruyuki Baba, Akio Suzuki, Hiromi Sawai, Masahiko Hayakawa, Noritaka Ishihara, Masashi Oota
  • Publication number: 20170256570
    Abstract: It is an object of the present invention to provide a semiconductor display device having an interlayer insulating film which can obtain planarity of a surface while controlling film formation time, can control treatment time of heating treatment with an object of removing moisture, and can prevent moisture in the interlayer insulating film from being discharged to a film or an electrode adjacent to the interlayer insulating film. An inorganic insulating film containing nitrogen, which is less likely to transmit moisture compared with an organic resin, is formed so as to cover a TFT. Next, an organic resin film containing photosensitive acrylic resin is applied to the organic insulting film, and the organic resin film is partially exposed to light to be opened. Thereafter, an inorganic insulting film containing nitrogen, which is less likely to transmit moisture compared with an organic resin, is formed so as to cover the opened organic resin film.
    Type: Application
    Filed: May 18, 2017
    Publication date: September 7, 2017
    Inventors: Shunpei YAMAZAKI, Satoshi MURAKAMI, Masahiko HAYAKAWA, Kiyoshi KATO, Mitsuaki OSAME
  • Publication number: 20170243981
    Abstract: Provided is a semiconductor device including a transistor having excellent electrical characteristics (e.g., on-state current, field-effect mobility, or frequency characteristics) or a semiconductor device including a transistor with high reliability. In the channel width direction of a channel-etched transistor in which an oxide semiconductor film is between first and second gate electrodes, the first and second gate electrodes are connected to each other through an opening portion in first and second gate insulating films. In addition, the first and second gate electrodes surround the oxide semiconductor film in a cross-section in the channel width direction, with the first gate insulating film provided between the first gate electrode and the oxide semiconductor film and the second gate insulating film provided between the second gate electrode and the oxide semiconductor film. Furthermore, the channel length of the transistor is 0.5 ?m or longer and 6.5 ?m or shorter.
    Type: Application
    Filed: March 6, 2017
    Publication date: August 24, 2017
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masahiko HAYAKAWA, Shinpei MATSUDA, Daisuke MATSUBAYASHI
  • Publication number: 20170236723
    Abstract: To suppress a change in electrical characteristics and to improve reliability in a semiconductor device using a transistor including an oxide semiconductor. The semiconductor device includes a gate electrode over an insulating surface, an oxide semiconductor film overlapping with the gate electrode, a gate insulating film which is between the gate electrode and the oxide semiconductor film and is in contact with a surface of the oxide semiconductor film, a protective film in contact with an opposite surface of the surface of the oxide semiconductor film, and a pair of electrodes in contact with the oxide semiconductor film. In the gate insulating film or the protective film, the amount of gas having a mass-to-charge ratio m/z of 17 released by heat treatment is greater than the amount of nitrogen oxide released by heat treatment.
    Type: Application
    Filed: May 2, 2017
    Publication date: August 17, 2017
    Inventors: Shunpei YAMAZAKI, Yasuharu HOSAKA, Toshimitsu OBONAI, Junichi KOEZUKA, Yukinori SHIMA, Masahiko HAYAKAWA, Takashi HAMOCHI, Suzunosuke HIRAISHI
  • Patent number: 9728556
    Abstract: A semiconductor device which includes an oxide semiconductor and in which formation of a parasitic channel due to a gate BT stress is suppressed is provided. Further, a semiconductor device including a transistor having excellent electrical characteristics is provided. The semiconductor device includes a transistor having a dual-gate structure in which an oxide semiconductor film is provided between a first gate electrode and a second gate electrode; gate insulating films are provided between the oxide semiconductor film and the first gate electrode and between the oxide semiconductor film and the second gate electrode; and in the channel width direction of the transistor, the first or second gate electrode faces a side surface of the oxide semiconductor film with the gate insulating film between the oxide semiconductor film and the first or second gate electrode.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: August 8, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hiroyuki Miyake, Kenichi Okazaki, Masahiko Hayakawa, Shinpei Matsuda
  • Publication number: 20170219959
    Abstract: A developing device includes a developer cartridge and a developing unit. The developer cartridge, in some instances, may include a shutter. This shutter may have a wall for closing a developer supply hole, and be movable, with respect to a developer cartridge casing, between an open position where the supply hole is opened by the wall and a closed position where the supply hole is closed by the wall. The shutter may further include a protrusion that is movable with respect to the wall of the shutter between a first position and a second position in an axial direction. The protrusion, in the first position, is engageable with a developing unit and, in the second position, would be disengaged from the developing unit.
    Type: Application
    Filed: April 12, 2017
    Publication date: August 3, 2017
    Inventors: Masahiko Hayakawa, Masashi Imai, Shougo Sato
  • Publication number: 20170213914
    Abstract: When a semiconductor device including a transistor in which a gate electrode layer, a gate insulating film, and an oxide semiconductor film are stacked and a source and drain electrode layers are provided in contact with the oxide semiconductor film is manufactured, after the formation of the gate electrode layer or the source and drain electrode layers by an etching step, a step of removing a residue remaining by the etching step and existing on a surface of the gate electrode layer or a surface of the oxide semiconductor film and in the vicinity of the surface is performed. The surface density of the residue on the surface of the oxide semiconductor film or the gate electrode layer can be 1×1013 atoms/cm2 or lower.
    Type: Application
    Filed: April 6, 2017
    Publication date: July 27, 2017
    Inventors: Shunpei YAMAZAKI, Masahiko HAYAKAWA, Tatsuya HONDA
  • Publication number: 20170162642
    Abstract: The present invention provides a TFT that has a channel length particularly longer than that of an existing one, specifically, several tens to several hundreds times longer than that of the existing one, and thereby allowing turning to an on-state at a gate voltage particularly higher than the existing one and driving, and allowing having a low channel conductance gd. According to the present invention, not only the simple dispersion of on-current but also the normalized dispersion thereof can be reduced, and other than the reduction of the dispersion between the individual TFTs, the dispersion of the OLEDs themselves and the dispersion due to the deterioration of the OLED can be reduced.
    Type: Application
    Filed: February 15, 2017
    Publication date: June 8, 2017
    Inventors: Makoto Udagawa, Masahiko Hayakawa, Jun Koyama, Mitsuaki Osame, Aya Anzai