Patents by Inventor Masahiko Hiratani

Masahiko Hiratani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6326218
    Abstract: Described is a manufacturing method of an integrated circuit which uses a thin film such as platinum or BST as a hard mask upon patterning ruthenium or the like, thereby making it possible to form a device without removing the hard mask. In addition, the invention method makes it possible to interpose a protecting film such as platinum in order to prevent, upon removing a resist used for the patterning of the hard mask, an underlying ruthenium film or the like from being damaged.
    Type: Grant
    Filed: May 22, 2000
    Date of Patent: December 4, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Yunogami, Kazuo Nojiri, Yuzuru Ohji, Sukeyoshi Tsunekawa, Masahiko Hiratani, Yuichi Matsui
  • Publication number: 20010038114
    Abstract: Plug electrodes of silicon are formed being buried in the through holes in a first insulating film, the plug electrodes being electrically connected to the source and drain regions of a MISFET on the main surface of a semiconductor substrate. Then, a second insulating film is deposited thereon and holes are formed therein such that the plug electrodes of silicon are exposed. A barrier film is formed on the surfaces of the silicon plugs, and in the holes are formed a dielectric to form lower electrodes of the capacitor elements and an upper electrode therefor.
    Type: Application
    Filed: February 5, 2001
    Publication date: November 8, 2001
    Inventors: Shinpei IIjima, Yoshitaka Nakamura, Masahiko Hiratani, Yuichi Matsui, Naruhiko Nakanishi
  • Publication number: 20010026988
    Abstract: In a semiconductor device including a plurality of memory cells, a deposition preventing film is formed on an interlayer insulating film in which a plurality of holes are formed, or a seed film is selectively formed on the interlayer insulating film and on an inner surface and a bottom surface of the holes. A film of Ru, Ir or Pt is deposited by chemical vapor deposition on the deposition preventing film, or on the interlayer insulating film by utilizing the seed film, under the condition where underlayer dependency occurs. In consequence, lower electrodes are formed in accordance with a pattern of the deposition preventing film or the seed film. A dielectric film is formed on the lower electrodes and the deposition preventing film at a predetermined temperature. The material of the lower electrodes does not lose conduction even when exposed to the predetermined temperature employed for forming the dielectric film. Upper electrodes are further formed on the dielectric film.
    Type: Application
    Filed: March 19, 2001
    Publication date: October 4, 2001
    Applicant: Hitachi, Ltd.
    Inventors: Yuichi Matsui, Masahiko Hiratani, Yasuhiro Shimamoto, Yoshitaka Nakamura, Toshihide Nabatame
  • Publication number: 20010023955
    Abstract: In a semiconductor device including a plurality of memory cells, a deposition preventing film is formed on an interlayer insulating film in which a plurality of holes are formed, or a seed film is selectively formed on the interlayer insulating film and on an inner surface and a bottom surface of the holes. A film of Ru, Ir or Pt is deposited by chemical vapor deposition on the deposition preventing film, or on the interlayer insulating film by utilizing the seed film, under the condition where underlayer dependency occurs. In consequence, lower electrodes are formed in accordance with a pattern of the deposition preventing film or the seed film. A dielectric film is formed on the lower electrodes and the deposition preventing film at a predetermined temperature. The material of the lower electrodes does not lose conduction even when exposed to the predetermined temperature employed for forming the dielectric film. Upper electrodes are further formed on the dielectric film.
    Type: Application
    Filed: March 19, 2001
    Publication date: September 27, 2001
    Applicant: Hitachi, Ltd.
    Inventors: Yuichi Matsui, Masahiko Hiratani, Yasuhiro Shimamoto, Yoshitaka Nakamura, Toshihide Nabatame
  • Patent number: 6144052
    Abstract: An oriented polycrystal silicon film or an amorphous silicon film 52 is disposed on the whole area beneath a conductive diffusion barrier 61 under a lower electrode of a ferroelectric capacitor. As a result, the conductive diffusion barrier, the lower electrode and the capacitor ferroelectric film become oriented films; therefore, it is possible to reduce the signal variation in capacitors even in minute semiconductor devices, and obtain a highly reliable semiconductor device.
    Type: Grant
    Filed: August 31, 1998
    Date of Patent: November 7, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Keiko Kushida, Masahiko Hiratani, Kazuyoshi Torii, Shinichiro Takatani, Hiroshi Miki, Yuuichi Matsui, Yoshihisa Fujisaki
  • Patent number: 5914068
    Abstract: Novel Bi-layer Perovskite ferroelectrics constituted of BiO intermediate layers (17) and pseudo-Perovskite layers (18) stacked alternately are disclosed. The Bi-layer Perovskite ferroelectrics have such a crystal structure which has a fundamental skeleton composed of each intermediate layer (17) consisting of one BiO plane and each pseudo-Perovskite structure (18) consisting of Pb(Zr, Ti)O.sub.3. Since the intermediate layer (17) is constituted of the BiO layer, the ferroelectrics are more excellent in ferroelectric characteristics and thermodynamic stability than known Perovskite ferroelectrics comprising a Bi.sub.2 O.sub.2 layer.
    Type: Grant
    Filed: December 30, 1996
    Date of Patent: June 22, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Masahiko Hiratani, Keiko Kushida, Kazushige Imagawa, Kazumasa Takagi
  • Patent number: 5380704
    Abstract: Disclosed herein is a superconducting field effect transistor (FET) which has at least an active region formed from a film of oxide normal conductor, a plurality of electrodes formed from a film of oxide superconductor, and a means to control the current which flows between the electrodes through the active region. Having a much greater electrode distance than the conventional superconducting device, it can be produced easily by lithography without resorting to special techniques.
    Type: Grant
    Filed: August 30, 1993
    Date of Patent: January 10, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Yoshinobu Tarutani, Tokuumi Fukazawa, Uki Kabasawa, Kazumasa Takagi, Akira Tsukamoto, Masahiko Hiratani, Toshikazu Nishino
  • Patent number: 5250506
    Abstract: A superconductive element at least comprising first and second superconductive electrodes composed of an oxide superconductor material and a semiconductor film composed of an oxide semiconductor material put between the first and second superconductive electrodes and disposed in adjacent with the first and the second superconductive electrodes, in which the semiconductor film is formed with an oxide comprising rare earth elements other than Pr, Ba and Cu as the main ingredient element or an oxide comprising predetermined amount of rare earth elements other than Pr, predetermined amount of Pr, Ba and Cu as the main ingredient element. Extremely fine size is no more necessary to enable fabrication with the existent fine fabrication technic.
    Type: Grant
    Filed: January 29, 1991
    Date of Patent: October 5, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Shinichiroh Saitoh, Yoshinobu Tarutani, Tokuumi Fukazawa, Masahiko Hiratani, Toshikazu Nishino, Haruhiro Hasegawa, Ushio Kawabe, Kazumasa Takagi, Mitsuo Suga
  • Patent number: 5151409
    Abstract: A superconducting oxide composition comprising Ln-Th-Cu-O wherein Ln indicates at least one element selected from a group consisting of Pr, Nd, Pm, Sm, Eu, Gd and Er. A superconducting structure is formed in such a manner that at least an insulating layer is sandwiched between two superconductor layers but the superconductor layers are electrically coupled with each other, and a superconducting device including the superconducting structure is constructed so as to perform a switching operation for an electric signal, to detect a light signal, and to detect the intensity of a magnetic field. Another superconducting device is formed so that two superconductor layers are put in direct contact with each other, and a tunnel current between the superconductor layers can be controlled.
    Type: Grant
    Filed: January 24, 1990
    Date of Patent: September 29, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Masahiko Hiratani, Shin'ichiro Saitoh, Katsuki Miyauchi, Tsuyoshi Seko
  • Patent number: 5077266
    Abstract: A weak-link Josephson junction is of the type employing a thin film of an oxide superconductor, in which a crystal grain boundary produced reflecting an artificial crystal defect is utilized as the weak-link junction. The crystal grain boundary is formed concretely by a method in which atoms of different species are deposited on the predetermined part of the surface of a substrate, the predetermined part of the surface of a substrate is disturbed, or parts of different crystal face orientations are formed at the surface of a substrate, whereupon the superconducting thin film is epitaxially grown on the substrate, or by a method in which the predetermined part of the superconducting thin film, epitaxially grown on a substrate, is diffused with atoms of different species hampering a superconductivity, or the predetermined part of the superconducting thin film is disturbed, whereupon the superconducting thin film is annealed.
    Type: Grant
    Filed: September 11, 1989
    Date of Patent: December 31, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Kazumasa Takagi, Tokuumi Fukazawa, Yoshimi Kawanami, Yuuichi Madokoro, Katsuki Miyauchi, Toshiyuki Aida, Yukio Honda, Masaaki Futamoto, Masahiko Hiratani
  • Patent number: 4645726
    Abstract: A compact, light-weight all solid state lithium battery is disclosed. The battery provides a good contact between a solid electrolyte and a Li anode by forming a Li alloy layer therebetween, even at the time of discharge at a large current density.
    Type: Grant
    Filed: November 21, 1985
    Date of Patent: February 24, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Masahiko Hiratani, Katsuki Miyauchi, Yukio Ito, Keiichi Kanehori, Fumiyoshi Kirino, Tetsuichi Kudo