Patents by Inventor Masahiko Kuraguchi

Masahiko Kuraguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200220002
    Abstract: According to one embodiment, a semiconductor device includes a first electrode extending along a first direction, a second electrode including a portion extending along the first direction, a third electrode extending along the first direction, a first member, first and second semiconductor regions, and a conductive portion. A position of the second electrode in a second direction is between the third electrode and the first electrode in the second direction crossing the first direction. A distance along the second direction between the third and second electrodes is shorter than a distance along the second direction between the second and first electrodes. The first member includes first and second regions. A conductivity of the second region is lower than a conductivity of the first region. The first semiconductor region includes Alx1Ga1-x1N. The second semiconductor region includes Alx2Ga1-x2N. A conductive portion is electrically connected to the first electrode.
    Type: Application
    Filed: September 10, 2019
    Publication date: July 9, 2020
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Aya SHINDOME, Masahiko Kuraguchi
  • Publication number: 20200220003
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first to fourth semiconductor regions, a first layer including, and a first insulating layer. The first semiconductor region includes Alx1Ga1-x1N and includes first to fifth partial regions. The third partial region includes a first element including at least one selected from the group consisting of Mg, Zn, and C. The second semiconductor region includes Alx2Ga1-x2N and includes a sixth partial region and a seventh partial region. The third semiconductor region includes Alx3Ga1-x3N and includes an eighth partial region and a ninth partial region. The fourth semiconductor region includes Alx4Ga1-x4N and includes a tenth partial region and an eleventh partial region. The first layer includes AlyGa1-yN and includes a first portion provided between the third partial region and the third electrode. The first insulating layer includes a second portion provided between the first portion and the third electrode.
    Type: Application
    Filed: September 10, 2019
    Publication date: July 9, 2020
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Masahiko Kuraguchi, Yosuke Kajiwara, Aya Shindome, Hiroshi Ono, Daimotsu Kato, Akira Mukai, Toshiki Hikosaka, Jumpei Tajima
  • Patent number: 10651307
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first to fifth layers, and an insulating portion. A position of the third electrode is between a position of the first electrode and a position of the second electrode. The first layer includes first to fifth partial regions. The first partial region is between the fourth and third partial regions. The second partial region is between the third and fifth partial regions. The second layer includes first and second semiconductor regions. The third layer is provided between the third partial region and the third electrode. The fourth layer is provided between the third partial region and the third layer. The fifth layer includes first and second intermediate regions. The third layer is provided between the first and second intermediate regions. The insulating portion includes a first insulating region provided between the third layer and the third electrode.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: May 12, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Jumpei Tajima, Toshiki Hikosaka, Masahiko Kuraguchi, Shinya Nunoue
  • Patent number: 10644143
    Abstract: According to one embodiment, a semiconductor device includes first and second semiconductor layers, first, second, and third electrodes, and first and second insulating portions. The first semiconductor layer includes first, second, and third semiconductor regions. The second semiconductor layer includes first to sixth partial regions. The first electrode is electrically connected to the first partial region. The second electrode is electrically connected to the second partial region. A position of the third electrode is between positions of the first and second electrodes in a second direction. A first direction crosses the second direction from the first to second semiconductor regions. The first insulating portion is provided between the third semiconductor region and the third electrode and between the third partial region and the third electrode in the first direction. The fourth partial region is between the second insulating portion and the second semiconductor region in the first direction.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: May 5, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Yosuke Kajiwara, Aya Shindome, Masahiko Kuraguchi
  • Publication number: 20200135870
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor member, drain electrodes, a drain interconnect portion, and a drain conductive portion. The semiconductor member includes first and second semiconductor regions. The drain electrodes extend along a first direction, are arranged in a second direction crossing the first direction, and are provided at the first semiconductor region. A direction from the first semiconductor region toward the second semiconductor region is aligned with the first direction. The drain interconnect portion extends along the second direction and is electrically connected to the drain electrodes. The drain conductive portion is electrically connected to the drain interconnect portion. The drain conductive portion includes first and second conductive regions. A portion of the drain interconnect portion is between the first conductive region and the first semiconductor region in a third direction.
    Type: Application
    Filed: September 10, 2019
    Publication date: April 30, 2020
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Yosuke Kajiwara, Aya Shindome, Masahiko Kuraguchi
  • Patent number: 10629724
    Abstract: According to one embodiment, a semiconductor device includes first, second and third electrodes, first, second, third, and fourth semiconductor regions, and an insulating portion. The first electrode includes first and second electrode portions. The first semiconductor region includes first, second, and third semiconductor portions. The first semiconductor portion is provided between the first electrode portion and the second electrode. The second semiconductor portion is provided between the second electrode portion and the third electrode. The third semiconductor portion is provided between the first and second semiconductor portions. The second semiconductor region is provided between the first semiconductor portion and the second electrode. The third semiconductor region is positioned between the second semiconductor region and the third electrode. The insulating portion includes first and second insulating regions.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: April 21, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenjiro Uesugi, Shigeya Kimura, Masahiko Kuraguchi
  • Publication number: 20200027977
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first to fifth layers, and an insulating portion. A position of the third electrode is between a position of the first electrode and a position of the second electrode. The first layer includes first to fifth partial regions. The first partial region is between the fourth and third partial regions. The second partial region is between the third and fifth partial regions. The second layer includes first and second semiconductor regions. The third layer is provided between the third partial region and the third electrode. The fourth layer is provided between the third partial region and the third layer. The fifth layer includes first and second intermediate regions. The third layer is provided between the first and second intermediate regions. The insulating portion includes a first insulating region provided between the third layer and the third electrode.
    Type: Application
    Filed: March 4, 2019
    Publication date: January 23, 2020
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Jumpei TAJIMA, Toshiki HIKOSAKA, Masahiko KURAGUCHI, Shinya NUNOUE
  • Publication number: 20200027976
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first to third layers, and a first insulating layer. The first layer includes first to fifth partial regions. The first partial region is between the fourth and third partial regions. The second partial region is between the third and fifth partial regions. The first insulating layer includes first and second inter-layer regions. The second layer includes first and second intermediate regions. The first intermediate region is provided between the first partial region and the first inter-layer region. The second intermediate region is provided between the second partial region and the second inter-layer region. The third layer includes first to third nitride regions. The first inter-layer region is between the first intermediate region and the first nitride region. The second inter-layer region is between the second intermediate region and the second nitride region.
    Type: Application
    Filed: March 11, 2019
    Publication date: January 23, 2020
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Akira MUKAI, Yosuke Kajiwara, Daimotsu Kato, Masahiko Kuraguchi
  • Publication number: 20200027978
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first and second semiconductor layers, a nitride layer, and an oxide layer. A direction from the second electrode toward the first electrode is aligned with a first direction. A position in the first direction of the third electrode is between the first electrode and the second electrode in the first direction. The first semiconductor layer includes first to fifth partial regions. The first partial region is between the fourth and third partial regions in the first direction. The second partial region is between the third and fifth partial regions in the first direction. The nitride layer includes first and second nitride regions. The second semiconductor layer includes first and second semiconductor regions. The oxide layer includes silicon and oxygen. The oxide layer includes first to third oxide regions.
    Type: Application
    Filed: March 5, 2019
    Publication date: January 23, 2020
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Yosuke KAJIWARA, Daimotsu KATO, Masahiko KURAGUCHI
  • Publication number: 20200006497
    Abstract: The nitride-based semiconductor device includes a carrier traveling layer 1 composed of non-doped AlXGa1-XN (0?X<1); a barrier layer 2 formed on the carrier traveling layer 1 and composed of non-doped or n-type AlYGa1-YN (0<Y?1, X<Y) having a lattice constant smaller than that of the carrier traveling layer 1; a threshold voltage control layer 3 formed on the barrier layer 2 and composed of a non-doped semiconductor having a lattice constant equal to that of the carrier traveling layer 1; and a carrier inducing layer 4 formed on the threshold voltage control layer 3 and composed of a non-doped or n-type semiconductor having a lattice constant smaller than that of the carrier traveling layer 1. The nitride-based semiconductor device further includes a gate electrode 5 formed in a recess structure, a source electrode 6 and a drain electrode 7.
    Type: Application
    Filed: September 11, 2019
    Publication date: January 2, 2020
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Masahiko KURAGUCHI
  • Publication number: 20190386127
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first and second semiconductor regions, and a first insulating film. The first semiconductor region includes a first partial region, a second partial region, a third partial region between the first and second partial regions, a fourth partial region between the first and third partial regions, and a fifth partial region between the third and second partial regions. The second semiconductor region includes a sixth partial region and a seventh partial region. The third electrode overlaps the sixth and seventh partial regions. The first insulating film includes a portion provided between the third electrode and the third partial region, between the third electrode and the fourth partial region, between the third electrode and the fifth partial region, between the third electrode and the sixth partial region, and between the third electrode and the seventh partial region.
    Type: Application
    Filed: March 11, 2019
    Publication date: December 19, 2019
    Applicants: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Daimotsu KATO, Toshiya Yonehara, Hiroshi Ono, Yosuke Kajiwara, Masahiko Kuraguchi, Tatsuo Shimizu
  • Patent number: 10505030
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, and first to third semiconductor regions. The third electrode is separated from the second electrode in a first direction. The first semiconductor region includes a first partial region separated from the first electrode, a second partial region separated from the second electrode, and a third partial region separated from the third electrode. The second semiconductor region includes a fourth partial region positioned between the first electrode and the first partial region, a fifth partial region positioned between the second electrode and the second partial region, and a sixth partial region positioned between the third electrode and the third partial region. The third semiconductor region includes a seventh partial region positioned between the second electrode and the fifth partial region and an eighth partial region positioned between the third electrode and the sixth partial region.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: December 10, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiki Hikosaka, Shigeya Kimura, Shinya Nunoue, Masahiko Kuraguchi
  • Publication number: 20190371928
    Abstract: According to one embodiment, a semiconductor device includes first and second regions, a first insulating portion, and first, second, and third electrodes. The first region includes first and second partial regions, and a third partial region between the first and second partial regions. The second region includes fourth and fifth partial regions. The fourth partial region overlaps the first partial region. The fifth partial region overlaps the second partial region. The first insulating portion includes first, second, and third insulating regions. The first insulating region is provided between the second insulating region and the third partial region and between the third insulating region and the third partial region. The first electrode is electrically connected to the fourth partial region. The second electrode is away from the first electrode and is electrically connected to the fifth partial region. The third electrode is provided between the first and second electrodes.
    Type: Application
    Filed: March 5, 2019
    Publication date: December 5, 2019
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Masahiko KURAGUCHI, Yosuke Kajiwara, Aya Shindome, Hiroshi Ono, Daimotsu Kato, Akira Mukai
  • Publication number: 20190371927
    Abstract: According to one embodiment, a semiconductor device includes first and second semiconductor layers, first, second, and third electrodes, and first and second insulating portions. The first semiconductor layer includes first, second, and third semiconductor regions. The second semiconductor layer includes first to sixth partial regions. The first electrode is electrically connected to the first partial region. The second electrode is electrically connected to the second partial region. A position of the third electrode is between positions of the first and second electrodes in a second direction. A first direction crosses the second direction from the first to second semiconductor regions. The first insulating portion is provided between the third semiconductor region and the third electrode and between the third partial region and the third electrode in the first direction. The fourth partial region is between the second insulating portion and the second semiconductor region in the first direction.
    Type: Application
    Filed: February 25, 2019
    Publication date: December 5, 2019
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Yosuke KAJIWARA, Aya Shindome, Masahiko Kuraguchi
  • Patent number: 10475915
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first layer, a second layer, a third layer, and an insulating layer. A position of the third electrode is between a position of the first electrode and a position of the second electrode. The first layer includes at least one of Alx1Ga1-x1N (0<x1<1) or p-type Alz1Ga1-z1N (0?z1<1) and has a first surface, a second surface, and a third surface. The second layer includes Alx2Ga1-x2N (0?x2<1 and x2<x1) and includes a first partial region, a second partial region, and a third partial region. The third layer includes Alx3Ga1-x3N (0<x3<1 and x2<x3) and includes a fourth partial region, a fifth partial region, and a sixth partial region.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: November 12, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Jumpei Tajima, Toshiki Hikosaka, Kenjiro Uesugi, Shigeya Kimura, Masahiko Kuraguchi, Shinya Nunoue
  • Patent number: 10453926
    Abstract: The nitride-based semiconductor device includes a carrier traveling layer 1 composed of non-doped AlxGa1-xN (0?X<1); a barrier layer 2 formed on the carrier traveling layer 1 and composed of non-doped or n-type AlYGa1-YN (0<Y?1, X<Y) having a lattice constant smaller than that of the carrier traveling layer 1; a threshold voltage control layer 3 formed on the barrier layer 2 and composed of a non-doped semiconductor having a lattice constant equal to that of the carrier traveling layer 1; and a carrier inducing layer 4 formed on the threshold voltage control layer 3 and composed of a non-doped or n-type semiconductor having a lattice constant smaller than that of the carrier traveling layer 1. The nitride-based semiconductor device further includes a gate electrode 5 formed in a recess structure, a source electrode 6 and a drain electrode 7.
    Type: Grant
    Filed: May 5, 2015
    Date of Patent: October 22, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Masahiko Kuraguchi
  • Patent number: 10431657
    Abstract: According to one embodiment, a semiconductor device includes first and second semiconductor regions, first to third electrodes, a conductive portion, first and second insulating layers. The first, second and third electrodes are separated from the first semiconductor region. The conductive portion is separated from the first semiconductor region. The second semiconductor region includes first to third partial regions. The first and second partial regions are electrically connected to the first and second electrodes, respectively. The third partial region is positioned between the second portion and the first semiconductor region. A portion of the first insulating layer is provided between the first portion and the first semiconductor region. The second insulating layer includes first and second insulating portions. The first insulating portion is positioned between the second portion and the third partial region.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: October 1, 2019
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Aya Shindome, Masahiko Kuraguchi, Tatsuo Shimizu
  • Publication number: 20190296111
    Abstract: In one embodiment, a semiconductor device is provided with a substrate, a first nitride semiconductor layer above the substrate, a second nitride semiconductor layer which is provided on the first nitride semiconductor layer and is in contact with the first nitride semiconductor layer, a source electrode provided between the substrate and the first nitride semiconductor layer and electrically connected to the first nitride semiconductor layer, a drain electrode provided on the second nitride semiconductor layer and electrically connected to the second nitride semiconductor layer, a gate insulating layer provided at least between the substrate and the first nitride semiconductor layer, a gate electrode between the substrate and the gate insulating layer, and a first insulating layer between the substrate and the gate insulating layer to cover the gate electrode and the source electrode.
    Type: Application
    Filed: August 31, 2018
    Publication date: September 26, 2019
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Jumpei Tajima, Toshiki Hikosaka, Kenjiro Uesugi, Masahiko Kuraguchi, Shinya Nunoue
  • Publication number: 20190288081
    Abstract: According to one embodiment, a semiconductor device includes first and second semiconductor regions, first to third electrodes, a conductive portion, first and second insulating layers. The first, second and third electrodes are separated from the first semiconductor region. The conductive portion is separated from the first semiconductor region. The second semiconductor region includes first to third partial regions. The first and second partial regions are electrically connected to the first and second electrodes, respectively. The third partial region is positioned between the second portion and the first semiconductor region. A portion of the first insulating layer is provided between the first portion and the first semiconductor region. The second insulating layer includes first and second insulating portions. The first insulating portion is positioned between the second portion and the third partial region.
    Type: Application
    Filed: August 7, 2018
    Publication date: September 19, 2019
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Aya SHINDOME, Masahiko KURAGUCHI, Tatsuo SHIMIZU
  • Publication number: 20190280112
    Abstract: A semiconductor device according to an embodiment includes a nitride semiconductor layer; an insulating layer; a first region disposed between the nitride semiconductor layer and the insulating layer and containing at least one element of hydrogen and deuterium; and a second region disposed in the nitride semiconductor layer, adjacent to the first region, and containing fluorine.
    Type: Application
    Filed: August 24, 2018
    Publication date: September 12, 2019
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Masahiko Kuraguchi, Toshiya Yonehara, Akira Mukai