Abstract: Proposed as a configuration, a controlling method, and a testing method for a ferroelectric shadow memory are (1) a bit line non-precharge method, in which no precharging of a bit line is performed during a read/write operation; (2) a plate line charge share method, in which electric charge is shared between plate lines that are driven sequentially during store/recall operation; (3) a word line boost method, in which the potential on a word line is raised during a write operation; (4) a plate line driver boost method, in which the driving capacity of a plate line driver is raised during a store/recall operation; and (5) a testing method for detecting a defect in a ferroelectric capacitor by arbitrarily setting a potential on a bit line from outside a chip.

Abstract: Proposed as a configuration, a controlling method, and a testing method for a ferroelectric shadow memory are (1) a bit line non-precharge method, in which no precharging of a bit line is performed during a read/write operation; (2) a plate line charge share method, in which electric charge is shared between plate lines that are driven sequentially during store/recall operation; (3) a word line boost method, in which the potential on a word line is raised during a write operation; (4) a plate line driver boost method, in which the driving capacity of a plate line driver is raised during a store/recall operation; and (5) a testing method for detecting a defect in a ferroelectric capacitor by arbitrarily setting a potential on a bit line from outside a chip.

Abstract: Proposed as a configuration, a controlling method, and a testing method for a ferroelectric shadow memory are (1) a bit line non-precharge method, in which no precharging of a bit line is performed during a read/write operation; (2) a plate line charge share method, in which electric charge is shared between plate lines that are driven sequentially during store/recall operation; (3) a word line boost method, in which the potential on a word line is raised during a write operation; (4) a plate line driver boost method, in which the driving capacity of a plate line driver is raised during a store/recall operation; and (5) a testing method for detecting a defect in a ferroelectric capacitor by arbitrarily setting a potential on a bit line from outside a chip.

Abstract: A TD converter is provided for digitally converting a delay time value into a digital value. In the TD converter, an oscillator circuit part inputs time domain data. A first-state counter circuit part measures a number of waves of an output oscillation waveform from the oscillator circuit part when time domain data is in a first state, and a second-state counter circuit part measures a number of waves of the output oscillation waveform from the oscillator circuit part when the time domain data is in a second state. An output signal generator part generates an output signal based on output count values of the first-state counter circuit part and the second-state counter circuit part, and a frequency control circuit controls the oscillator circuit part to always oscillate and to control an oscillation frequency of the oscillator circuit part.

Abstract: Provided is memory which is capable of dynamically changing memory cell bit reliability and of switching the operating mode so as to accommodate process variations, thereby reducing the operating voltage. The memory is provided with a mode control line selection circuit for dividing mode control lines in to word units and using control line selection signals and global control signals to control the mode control lines divided into word units, and a word line selection circuit for dividing the word lines that control the conduction of switching unit into word units and using word line selection signals and global word signals to control the word lines divided into word units. The mode control line switching circuit is used to switch between a 1 bit/1 cell mode and a 1 bit/n cell mode in word units.

Abstract: A sensor network system including node devices connected in a network via predetermined propagation paths collects data measured at each node device to be aggregated into one base station via a time-synchronized sensor network system. The base station calculates a position of the signal source based on the angle estimation value of the signal from each node device and position information thereof, designates a node device located nearest to the signal source as a cluster head node device, and transmits information of the position of the signal source and the designated cluster head node device to each node device, to cluster each node device located within the number of hops from the cluster head node device as a node device belonging to each cluster. Each node device performs an emphasizing process on the received signal from the signal source, and transmits an emphasized signal to the base station.

Abstract: Provided is memory which is capable of dynamically changing memory cell bit reliability and of switching the operating mode so as to accommodate process variations, thereby reducing the operating voltage. The memory is provided with a mode control line selection circuit for dividing mode control lines in to word units and using control line selection signals and global control signals to control the mode control lines divided into word units, and a word line selection circuit for dividing the word lines that control the conduction of switching unit into word units and using word line selection signals and global word signals to control the word lines divided into word units. The mode control line switching circuit is used to switch between a 1 bit/1 cell mode and a 1 bit/n cell mode in word units.

Abstract: An AD converter includes a VT converter circuit part which inputs an analog input voltage and a sampling clock, converts the analog input voltage to a corresponding delay time, and outputs time domain data. A ring oscillator circuit part of N stages inputs the time domain data, and an error propagation circuit part takes out delay information containing a quantization error from phase information of the ring oscillator circuit part of the previous stage, and propagate the delay information to the ring oscillator circuit part of a subsequent stage. A counter circuit part measures a number of waves of an output oscillation waveform of the ring oscillator circuit part of each stage, and an output signal generator part generates an output signal from an output counted value of each counter circuit part. A reset part resets each error propagation circuit part and each counter circuit part with a sampling clock.

Abstract: A sensor network system including node devices connected in a network via predetermined propagation paths collects data measured at each node device to be aggregated into one base station via a time-synchronized sensor network system. The base station calculates a position of the signal source based on the angle estimation value of the signal from each node device and position information thereof, designates a node device located nearest to the signal source as a cluster head node device, and transmits information of the position of the signal source and the designated cluster head node device to each node device, to cluster each node device located within the number of hops from the cluster head node device as a node device belonging to each cluster. Each node device performs an emphasizing process on the received signal from the signal source, and transmits an emphasized signal to the base station.

Abstract: It is aimed to provide a semiconductor memory device capable of solving a half-select problem in 8Tr SRAMs and, simultaneously, achieving a reduction in charge/discharge power in a half-selected column, which has been a problem with the conventional write-back scheme. An 8Tr SRAM includes 1) a bitline half driver circuit which is capable of reading retention data from read bitline (RBL) of each memory cell of a memory cell group in a column direction and drives the write bitlines only for the memory cells of a half-selected column according to the read data, 2) a selection signal circuit to which an enable signal and a column selection signal of the bitline half driver circuit are input and which activates the bitline half driver circuit, and 3) an equalizer circuit which equalizes the write bitlines of the memory cell group in the column direction and does not precharge the write bitlines.

Abstract: An AD converter includes a VT converter circuit part which inputs an analog input voltage and a sampling clock, converts the analog input voltage to a corresponding delay time, and outputs time domain data. A ring oscillator circuit part of N stages inputs the time domain data, and an error propagation circuit part takes out delay information containing a quantization error from phase information of the ring oscillator circuit part of the previous stage, and propagate the delay information to the ring oscillator circuit part of a subsequent stage. A counter circuit part measures a number of waves of an output oscillation waveform of the ring oscillator circuit part of each stage, and an output signal generator part generates an output signal from an output counted value of each counter circuit part. A reset part resets each error propagation circuit part and each counter circuit part with a sampling clock.

Abstract: A digital VLSI circuit is provided with functions in which the number of switching operations to supply electric power to each arithmetic operation unit is reduced in a restricted period of time while electric power supply is controlled for each arithmetic operation unit, so that low power consumption can be achieved in real pipe-line arithmetic operation.

Abstract: A memory wherein the bit reliability of the memory cells can be dynamically varied depending on the application or the memory status, the operation stability is ensured, and thereby a low power consumption and a high reliability are realized. Either a mode (a 1-bit/1-cell mode) in which one bit is composed of one memory cell or a mode (a 1-bit/n-cell mode) in which one bit is composed of n (n is two or more) connected memory cells is dynamically selected. When the 1-bit/n-cell mode is selected, the read/write stability of one bit is enhanced, the cell current during read is increased (read is speeded up), and a bit error, if occurs, is self-corrected. Especially, a pair of CMOS transistors and a control line for performing control so as to permit the CMOS transistors to conduct are added between the data holding nodes of n adjacent memory cells. With this, the word line (WL) is controlled, and thereby the operation stability is further improved.

Abstract: A circuit startup method utilizing utterance estimation in a speech processing system including a sound collecting device is provided. The circuit startup method includes a subset power supply step of supplying power to the sound collecting device and a signal processing circuit, and a sound collecting step of inputting a sound from the sound collecting device through the signal processing circuit. The circuit startup method further includes an utterance estimation step of estimating whether or not a speech is contained in the inputted sound, and a power supply step of supplying power to the speech processing circuit for an utterance interval when it is estimated that a speech is contained from an estimation result of the utterance estimation step.

Abstract: A memory wherein the bit reliability of the memory cells can be dynamically varied depending on the application or the memory status, the operation stability is ensured, and thereby a low power consumption and a high reliability are realized. Either a mode (a 1-bit/1-cell mode) in which one bit is composed of one memory cell or a mode (a 1-bit/n-cell mode) in which is composed of n (n is two or more) connected memory cells is dynamically selected. When the 1-bit/n-cell mode is selected, the read/write stability of one bit is enhanced, the cell current during read is increased (read is speeded up), and a bit error, if occurs, is self-corrected. Especially, a pair of CMOS transistors and a control line for performing control so as to permit the CMOS transistors to conduct are added between the data holding nodes of n adjacent memory cells. With this, the word line is controlled, and thereby the operation stability is further improved.

Abstract: A motion estimation method capable of reducing the amount of calculation as compared to a full search method. In the method, a coarse search block and fine search blocks are defined. The fine search blocks are given by dividing the coarse search block into a plurality of blocks so that the fine search blocks are contained in the coarse search block. A sparsely interpolated image and a densely interpolated image are defined. A first search is performed using the defined coarse search block and the defined sparsely interpolated image. A second search is performed using the defined coarse search block and the defined densely interpolated image. With regard to search blocks belonging to the fine search blocks, only a surrounding region of an optimal point obtained in the first search is searched.

Abstract: A digital VLSI circuit is provided with functions in which the number of switching operations to supply electric power to each arithmetic operation unit is reduced in a restricted period of time while electric power supply is controlled for each arithmetic operation unit, so that low power consumption can be achieved in real pipe-line arithmetic operation.

Abstract: [Task] A motion picture encoding/decoding system and a motion picture encoding/decoding method which are capable of allowing decrease of power consumption are provided. [Means of solution] The system and the method are severally provided with a processor 1, a means of calculating necessary operation volume 2 for calculating the volume of operation necessary for encoding/decoding the present frame, and a means of calculating power-supply voltage, substrate bias voltage and operating frequency 3 for calculating a power-supply voltage and a substrate bias voltage and an operating frequency which are capable of encoding/decoding the necessary operation volume within the time allocated in advance to the process of encoding/decoding the present frame. The processor 1 performs the process of encoding/decoding the present frame while operating steadily with the operating frequency and the power-supply voltage and the substrate bias voltage calculated as mentioned above.

Abstract: In an encoding method of moving pictures which generates a predictive picture for a current picture based on a reference picture and a motion vector, a macroblock is divided into subblocks. In each of the plurality of subblocks, an initial value of the motion vector is set and an evaluated value E on a difference between the current picture and the reference picture is calculated along a steepest descent direction to determine the minimum value. Then, the smallest evaluated value is selected among the minimum values obtained on the plurality of subblocks to determine the motion vector based on the pixel position of the smallest value.

Abstract: An encoding preprocessing part 1 extracts the amount of image feature relative to image data and passes the amount of image feature to a control part 2 as image feature amount information 11 and also sends image data 10 to an encoding part 3. The control part 2 determines whether there is a dissolve image or not based on the image feature amount information 11 and if it is determined that the image data 10 is the dissolve image, an encoding parameter 12 is set so that a configuration of GOP which is normally M=3 is changed into the configuration of GOP of M=2, and the encoding part 3 performs encoding based on the encoding parameter 12. As a result of that, a prediction error of a B-picture frame in a dissolve interval becomes substantially zero and on encoding in the dissolve interval, the amount of information occurrence in frames except I-picture and P-picture frames can be reduced and thus the amount of information occurrence as a whole can be reduced.