Abstract: This invention is aimed at providing a motion picture encoding or decoding system and a motion picture encoding or decoding method which economize the electric power consumption efficiently as compared with the conventional technique. They are provided with at least one failure avoiding means adapted to calculate a necessary volume Kp of operation required for encoding or decoding one frame, decide an operating frequency F capable of encoding or decoding the necessary volume Kp of operation within a duration Te allocated in advance to the operation of encoding or decoding the one frame, perform the operation of encoding or decoding the one frame while continuing the operation of the processor at the operating frequency F and an operating voltage V befitting the operating frequency F, and avoid the failure situation which occurs when the necessary volume Kp of operation is smaller than the actually necessary volume of operation.

Abstract: An information processing apparatus includes memory for storing a plurality of data; updating means for updating data stored in the memory in a transaction; and setting means for setting, with regard to each of the plurality of data stored in the memory, whether updated data updated by the updating means is to be validated or invalidated at abortion of the transaction, respectively. The setting means performs its setting in advance of the transaction. Saving means saves data, for which updated data has been set to be invalidated at abortion of the transaction by the setting means, except for data for which updated data has been set to be validated at abortion of the transaction by the setting means, before execution of data update by the updating means in the transaction.

Abstract: In an encoding method of moving pictures which generates a predictive picture for a current picture based on a reference picture and a motion vector, a macroblock is divided into subblocks. In each of the plurality of subblocks, an initial value of the motion vector is set and an evaluated value E on a difference between the current picture and the reference picture is calculated along a steepest descent direction to determine the minimum value. Then, the smallest evaluated value is selected among the minimum values obtained on the plurality of subblocks to determine the motion vector based on the pixel position of the smallest value.

Abstract: An encoding preprocessing part 1 extracts the amount of image feature relative to image data and passes the amount of image feature to a control part 2 as image feature amount information 11 and also sends image data 10 to an encoding part 3. The control part 2 determines whether there is a dissolve image or not based on the image feature amount information 11 and if it is determined that the image data 10 is the dissolve image, an encoding parameter 12 is set so that a configuration of GOP which is normally M=3 is changed into the configuration of GOP of M=2, and the encoding part 3 performs encoding based on the encoding parameter 12. As a result of that, a prediction error of a B-picture frame in a dissolve interval becomes substantially zero and on encoding in the dissolve interval, the amount of information occurrence in frames except I-picture and P-picture frames can be reduced and thus the amount of information occurrence as a whole can be reduced.

Abstract: When a server receives a service request from a client, identifiers of a terminal and of a user are acquired from the service request and authority with respect to the service request is uniquely decided from the terminal and user identifiers acquired. It is then determined, using the authority decided, whether or not to accept the service request.

Abstract: This invention is to autonomously control reduction of wide-area traffic by sharing the same stream among nodes while avoiding distribution route localization due to route selection at the network level, and efficiently distribute a real-time data stream maintaining a high quality. In a real-time data distribution control system for distributing real-time data such as image or audio data using a network, node devices having data transmission/reception/relay means are put into groups. When the real-time data distribution route is to be selected among the node groups, an upper node group is selected in units of transmission sources.

Abstract: An information processing apparatus manages the correspondence between identification information, which is for identifying a plurality of transactions within one process, and the transactions. To this end, the information processing apparatus operates on the identification information by operations including creation, cancellation and switching of the identification information. The creation, cancellation and switching of the identification information then results in the corresponding operation on the respective transaction.

Abstract: An arrangement for executing a process in a data processing system using first and second programs each including executable codes and data in coordinated fashion in which a portion of the data and executable codes from the first program is provided to the second program during execution of the process. In execution of the process, portions of the data and executable codes provided by the first program to the second program are forcibly added or forcibly substituted and executed by the second program. The data and executable code portions are provided by injection and the injection and execution are conducted by imparting an acknowledgement of the addition or substitution and execution to the first program by the second program.

Abstract: A serial access memory device is disclosed in which order of access to writing and reading memory cell columns can be controlled. A writing column selecting circuit and a reading column selecting circuit are each comprised of ring pointers with a controllable number of stages. The number of stages of the ring pointers is controlled in response to control signals stored in a serial interface circuit. As a result, two ring pointers each having two stages are formed in the writing column selecting circuit while one ring pointer having four stages is formed in the reading column selecting circuit. After two data signals are written in selected two memory cell columns in parallel, written data signals are read out from serially selected four memory cell columns at a speed twice that in the writing. This serial access memory device is applied to a progressive scan conversion circuit for video signal processing.

Abstract: According to a data management method of managing shared data which is shared by a plurality of processes and data inherent in a process which exists during execution of one particular process and disappears when the process is finished, when each process fetches shared data from a data base into a memory, whether the shared data requires data inherent in the process is checked. Any inherent data of the process is determined, if necessity for that data is determined. The determined inherent data of the process is stored in the memory. A pointer for the inherent data of the process, which is stored in the memory, is stored into the fetched shared data in accordance with attributes inherent in the process requiring the inherent data of the process.

Abstract: A technique for reducing the circuit area of a test circuit which is formed by a parallel register which includes a plurality of scan latch circuits is disclosed. A scan latch circuit is formed by a master-slave latch circuit. The master-slave latch circuit includes a static latch circuit which serves as a master side latch circuit and a dynamic latch circuit which serves as a slave side latch circuit. Under the control of a control signal, either a signal inputted to a first circuit part or a signal inputted to a preceding stage scan latch circuit is held in the static latch circuit. The signal which was inputted to a first circuit part is outputted via an output terminal of the scan latch circuit to a second circuit part. The signal which was inputted to the preceding stage scan latch circuit is advanced to the dynamic latch circuit and thereafter outputted to a next scan latch circuit via other output terminal of the scan latch circuit.

Abstract: The semiconductor test system comprises an OBIC measuring device (8) and a tester (5). The tester (5) transmits a test signal to an input pad (2a) of a semiconductor integrated circuit (1). In synchronization with this, the OBIC measuring device (8) irradiates drain regions (6) of the semiconductor integrated circuit (1) with a laser beam (7) one after another, to thereby detect the generation of the OBIC. An comparator (5c) in the tester (5) compares an output signal from an output pad (2b) of the semiconductor integrated circuit (1) and an OBIC detection signal from the OBIC measuring device (8) with expected values (5b).

Abstract: A read only memory includes a memory cell provided at an intersection between a word line and a bit line, and a plurality of reference potential transmission lines each receiving a reference potential determined in accordance with an externally applied potential designating signal. The memory cell includes a transistor element having a gate coupled to a word line, a drain coupled to a bit line and a source which is coupled to one of the reference potential transmission lines or is held in an open state. Stored data in the memory cell is changed by switching the potentials of the reference potential transmission lines. This enables storing of different data bits in one memory cell.

Abstract: A semiconductor integrated circuit device includes a memory cell array for storing data to be processed, and an operational unit for effecting a predetermined operation on the data read from the memory cell array. The memory cell array has first and second regions for storing first and second data words of first and second groups. The first data words and second data words each include a plurality of data bits. The first region includes a plurality of bit arrays for storing data bits of the same digit in the first data words, and the second region includes a plurality of bit arrays for storing data bite of the same digit in the second data words. The bit arrays of the first and second groups are arranged alternately in the order of digits of the data words. The bit arrays storing the data bits of the same digit form one subarray. The data bits in one data word are stored in the same positions of the bit arrays. The operational unit includes operational circuits each corresponding to one of the subarrays.

Abstract: A DRAM having a data preset function is disclosed. A memory cell includes connectors which are formed of contact holes or through holes and which can be selectively formed in order to program preset data. For example, when preset data "0" is programmed, connectors are formed, and connector 17 is not formed. When a data precharge signal of a high level is applied, a transistor is turned on and as a result, a data storage capacitor is discharged. In other words, predetermined data is written into capacitor. Thus, the DRAM having the data preset function is provided.

Abstract: Each of memory cells of a semiconductor memory device comprises a transistor connected between a node and a node, a transistor connected between the node and a node, a transistor connected between a node and a node, and a transistor connected between node and a node. Each of the nodes is connected to either of a first potential line and a second supply line in a program unit when it is manufactured, and each of the nodes is connected to either of the first and the second ground lines in a program unit when it is manufactured.A supply potential is supplied to the first supply line, and the supply potential or the ground potential is selectively supplied to the second supply line. The ground potential is supplied to the first ground line, and the ground potential or the supply potential is selectively supplied to the second ground line.

Abstract: A read only memory includes a memory cell provided at an intersection between a word line and a bit line, and a plurality of reference potential transmission lines each receiving a reference potential determined in accordance with an externally applied potential designating signal. The memory cell includes a transistor element having a gate coupled to a word line, a drain coupled to a bit line and a source which is coupled to one of the reference potential transmission lines or is held in an open state. Stored data in the memory cell is changed by switching the potentials of the reference potential transmission lines. This enables storing of different data bits in one memory cell.

Abstract: An integrated circuit 1 for video signal processing comprises a 2-line memory 3, a video signal processing circuit 4 and a coincidence circuit 6. A digital video signal of 8 bits inputted to an input terminal group 2 is applied to the 2-line memory 3 and the coincidence circuit 6. Also, the 2-line delay signal of 8 bits outputted from the 2-line memory 3 is applied to the coincidence circuit 6. The coincidence circuit 6 determines coincidence or non-coincidence of the input digital video signal and the 2-line delay signal received and outputs the result of that determination through a coincidence output terminal. As a result, an operation of the 2-line memory 3 can be tested individually.

Abstract: An image processing apparatus for digitizing an analog image by dispersing the digitizing error to the surrounding areas. The characteristics or edge of the analog imnage are identified, and the error dispersing area is varied according to the result of identification, thus enabling reproduction of the image with high quality regardless of the nature of the original image.

Abstract: First-In First-Out (FIFO) memory device is disclosed. A ring pointer circuit sequentially and repeatedly selects memory cells in a memory cell array. When it is detected that a defective memory cell exists on a memory cell row, selection of that memory cell row is invalidated by the ring pointer circuit by cutting off a laser trimming line. In addition, by selectively cutting off laser trimming lines in a switching circuit and a redundancy ring pointer circuit, a redundancy memory cell row is selectively added in place of the defective memory cell row. Accordingly, stages required for the ring pointer circuit are maintained. In other words, the FIFO memory device having a defective memory cell is saved, resulting in improvement in yield in the manufacture.