Abstract: First and second supply lines are connected to some or all of a plurality of memory cells included in a memory cell array. Only the first supply line is connected to the remaining memory cells. When a voltage of H level is supplied to the first and second supply lines, all memory cells function as SRAM memory cells in which stored information can be rewritten. Meanwhile when H level is applied to the first supply line and L level is applied to the second supply lines, memory cells to which both the first and second supply lines are connected are set to a state in which information of the logic "1" or "0" is fixedly stored. Namely, they function as ROM memory cells. At this time, the remaining member cells to which only the first supply line is connected function as SRAM memory cells. In this manner, by switching the voltages applied to the second supply line, some or all of the memory cell arrays function as SRAM or ROM.

Abstract: The dynamic semiconductor memory device comprises a plurality of write block selecting lines and a plurality of read block selecting lines for selecting any one of the memory cell groups, a plurality of write row selecting lines for selecting any memory cells for a word in one of the memory cell groups selected by the write block selecting lines, a purality of first logic gates connected at one input terminals thereof to the write block selecting lines and at the other input terminals thereof to the write row selecting lines, a plurality of divisional write word lines each connecting an output terminal of one of the first logic gates in parallel to the corresponding memory cells for a word, a plurality of read row selecting lines for selecting any memory cells for a word in one of the memory cell groups selected by the read block selecting lines, a plurality of second logic gates connected at one input terminals thereof to the read block selecting lines and at the other input terminals thereof to the read row

Abstract: An FIFO memory comprises two-transistor type memory cells. Each of the memory cells comprises a first transistor, a second transistor and storage capacitance. The storage capacitance is connected to a first bit line through the first transistor and connected to a second bit line through the second transistor. The first transistor has its gate connected to a first word line, and the second transistor has its gate connected to a second word line. Data is written or read out through the first transistor, and data is read out or written through the second transistor.

Abstract: A variable length shift register comprises a memory cell array (1) having memory cells arranged in a matrix of row and columns, a variable length ring pointer (2) responsive to a bit length selecting signal for sequentially activating a single row in the memory cell array in a recirculated manner within a predetermined constant range, an input buffer (4) for writing data into a memory cell of the activated row, and an output buffer (5) for reading out data from a memory cell of the activated row.

Abstract: An address counter (2) counts the clock pulses sequentially to provide a count value as an address signal to a coincidence detecting circuit (3) and decoder (4). The coincidence detecting circuit (3) compares delay data applied from a delay data generating circuit (8) with the address signal and applies a reset signal to the address counter (2) when they coincide with each other. The address counter (2) repeats sequentially the above-mentioned operation in response to the reset signal after the count of address is reset to a predetermined value. The decoder (4) specifies a memory cell comprised in a memory device for performing a reading and writing operation in response to the address signal. The data output circuit (6) and the data input circuit (5) perform the reading and writing operation sequentially to the specified memory cell in response to the control signal outputted from the control circuit (7). As a result, the input data previously written is read and outputted with a delay.

Abstract: A memory cell array (61) comprises a plurality of three-transistor type memory cells (10) arranged in a plurality of rows and columns. A plurality of pairs of write bit lines (WB1, WB2) and a plurality of read bit lines (RB) are provided corresponding to each column of the memory cell array (61). The plurality of write word lines (WWL) and the plurality of read word lines (RWL) are provided corresponding to each row of the memory cell array (61). Information is written to memory cells (10) in odd rows through the respective one write bit lines of the pairs of write bit lines (WB1, WB2), and information is written to memory cells (10) in even rows through the respective other write bit lines of the pairs of write bit lines (WB1, WB2). A sense amplifier (30) is connected to each of the pairs of write bit lines (WB1, WB2). At the time of write operation, refresh operation is performed by the sense amplifier (30) with respect to memory cells (10) in non-selected columns.

Abstract: An integrated circuit 1 for video signal processing includes a 2-line memory 3, a video signal processing circuit 4 and a coincidence circuit 6. A digital video signal of 8 bits inputted to an input terminal group 2 is applied to the 2-line memory 3 and the coincidence circuit 6. Also, the 2-line delay signal of 8 bits outputted from the 2-line memory 3 is applied to the coincidence circuit 6. The coincidence circuit 6 determines coincidence or non-coincidence of the input digital video signal and the 2-line delay signal received and outputs the result of that determination through a coincidence output terminal. As a result, an operation of the 2-line memory 3 can be tested individually.

Abstract: There is an image processing apparatus for digitally processing an image. This apparatus comprises: a binarization circuit to binarize image data by a predetermined threshold value; a processor to correct errors generated in binarization; a first detector to detect an edge direction of the image from the image data; and a second detector to detect an edge quantum of the image from the image data. The process corrects the error data in accordance with the edge direction detected by the first detector or the edge quantum detected by the second detector. The errors to be corrected by the processor are the errors between the output concentration data after the binarization and the image concentration data. The processor adds weight coefficients to the error data in a predetermined range stored in a memory and then adds the weighted error data to image data to be newly binarized. The sum of the weight coefficients which are used in the weighting process is set to "1".

Abstract: An image processing apparatus for digitizing an analog image by dispersing the digitizing error to the surrounding areas. The characteristics or edge of the analog image are identified, and the error dispersing area is varied according to the result of identification, thus enabling reproduction of the image with high quality regardless of the nature of the original image.

Abstract: A first memory cell array (84) has an even address space and a second memory cell array 94 has an odd address space. The memory cell arrays (84, 94) are alternately accessed by even address signals generated from an address counter (81) and odd address signals generated from an address counter (91) so that the data stored in the memory cell arrays are alternately read while new input data are written in the accessed memory cells.

Abstract: A semiconductor integrated circuit has a plurality of circuits (2 and 5) to be tested for verification of operation thereof and first, second and third scanning registers (1, 4 and 6) to be used for self-testing, and it further has a register (3) for delay. In operation, predetermined test data is inputted to each of the first and second scanning registers (1and 4) and then the first and second circuits (2 and 5) to be tested process those data simultaneously. Thus, testing time is saved. Although the time required for processing in the first circuit (2) to be tested is shorter than that in the second circuit (5) to be tested, the processed data can be obtained simutaneously by the delay function of the register (3).

Abstract: A power supply voltage to be applied to a metallic connection 36a is supplied through an n.sup.+ diffusion region 34a, an N type well 22, an n.sup.+ diffusion region 34c and a metallic connection 36C to a p.sup.+ diffusion region 23b serving as a power supply line. An n.sup.+ diffusion region 73 serving as a ground line is grounded through a metallic connection 76c, a p.sup.+ diffusion region 74c, a P type well 72, a p.sup.+ diffusion region 74b and a metallic connection 76b.

Abstract: A redundancy-secured semiconductor memory including a matrix of regular memory cells consisting of a plurality of regular memory cell trains, an extra memory cell train for redundant construction, and a taking-over system for enabling the extra memory cell train to take over the function of a faulty regular memory cell train including a faulty bit, wherein the taking-over system comprises a decoder and a monostable latching circuit connected to the decoder through a current conducting element capable of breakage in response to when one of the regular memory cell trains comes to include a faulty bit, thereby enabling the monostable latching circuit to fix its output to the low logic potential. Thus, the faulty regular memory cell train is kept in an unselected state without DC power consumption.

Abstract: A memory matrix is segmented in the direction of columns into a plurality of groups of memory cells. The memory cells are accessible through respective preceding word lines each of which is provided for each of the rows of the matrix and commonly to all of the groups of the memory cells and group word lines each of which is provided per group and per row, so that a path for column current is set up during access time only in the column which belongs to a particular group including a particular memory to be accessed.

Abstract: A semiconductor memory device is improved as regards current consumption and access time by dividing the memory cells into a plurality of columner groups and providing group selecting lines. Front-end word lines of low resistance are connected to outputs of row decoders, and AND gates receive selecting signals on the group selecting lines and the outputs of the front-end word lines. Word lines of a comparatively short length are connected to the AND outputs.

Abstract: A differential amplifying circuit includes a pair of main amplifying circuits (5a, 5b) each having at least three input terminals and at least one output terminal, and a pair of auxiliary amplifying circuits (6a, 6b) each having at least one input terminal. Complimentary inputs (D1, D1) are connected to the input terminals of said pair of auxiliary amplifying circuits (6a, 6b), the outputs (D2, D2) of the main amplifying circuits (5a, 5b) are connected as crossing feedback inputs to at least a pair of input terminals of said pair of main amplifying circuits (5a, 5b), the complimentary inputs (D2, D2) are also connected to the other at least one pair of input terminals, and the outputs of said auxiliary amplifying circuits (6a, 6b) are further connected to the further at least pair of input terminals.

Abstract: A semiconductor memory device is improved as regards current consumption and access time by dividing the memory cells into a plurality of columner groups and providing group selecting lines. Front-end word lines flow resistance are connected to outputs of row decoders, and AND gates receive selecting signals on the group selecting lines and the outputs of the front-end word lines. Word lines of a comparatively short length are connected to the AND outputs.

Abstract: A memory matrix is segmented in the direction of columns into a plurality of groups of memory cells. The memory cells are accessible through respective preceding word lines each of which is provided for each of the rows of the matrix and commonly to all of the groups of the memory cells and group word lines each of which is provided per group and per row, so that a path for column current is set up during access time only in the column which belongs to a particular group including a particular memory to be accessed.