Patents by Inventor Masahiro Miyata

Masahiro Miyata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5705230
    Abstract: The improved method comprises contacting a substrate 5 at least once by a liquid containing the elements that compose a pure metal or an alloy with which the small holes or recesses 3a in the substrate 5 are to be filled or covered, whereby the liquid wets the inner surfaces of said small holes or recesses 3a while, at the same time, said pure metal or said alloy is deposited on the surface of said substrate 5. The method is capable of filling small holes or covering small recesses in the surface of the substrate 5 with improved efficiency while, at the same time, it improves the heat resistance and materials stability of the part that contains the formed filling or covering layer.
    Type: Grant
    Filed: October 17, 1994
    Date of Patent: January 6, 1998
    Assignee: Ebara Corporation
    Inventors: Toru Matanabe, Hirokazu Ezawa, Masahiro Miyata, Yukio Ikeda, Manabu Tsujimura, Hiroaki Inoue, Takeyuki Odaira, Naoaki Ogure
  • Patent number: 5656542
    Abstract: In a semiconductor device and a method for manufacturing the same according to the present invention, for example, an insulating film is deposited on a silicon substrate, and a concave groove is formed in the insulating film in accordance with a predetermined wiring pattern. Titanium and palladium are deposited in sequence on the insulating film to form a titanium film and a palladium film, respectively. A silver film is formed on the palladium film by electroplating, and a groove-shaped silver wiring layer is formed by polishing. The resultant structure is annealed at a temperature of about 700.degree. C., and an intermetallic compound is formed by alloying the titanium film and palladium film with each other. Consequently, a burying type wiring layer whose resistance is lower than that of aluminum, is constituted by the silver wiring layer and intermetallic compound.
    Type: Grant
    Filed: October 18, 1995
    Date of Patent: August 12, 1997
    Assignees: Kabushiki Kaisha Toshiba, Ebara Corporation
    Inventors: Masahiro Miyata, Hirokazu Ezawa, Naoaki Ogure, Manabu Tsujimura, Takeyuki Ohdaira, Hiroaki Inoue, Yukio Ikeda
  • Patent number: 5529634
    Abstract: An evaporation chamber for forming fine metal particles is separated from a film formation chamber in which the substrate having a metal film such as a metal column thereon is placed during metal film deposition. The pressure of the film formation chamber is set to be lower than that of the evaporation chamber, and the fine metal particles are sprayed on the substrate by the pressure difference to form the metal column. Therefore, a wiring layer, a connection electrode for connecting the wiring layer to another wiring layer, and the like can easily be formed by a small number of steps.
    Type: Grant
    Filed: April 19, 1995
    Date of Patent: June 25, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiro Miyata, Hidemitsu Egawa, Johta Fukuhara, Shinzi Takeda, Hirokazu Ezawa
  • Patent number: 5500559
    Abstract: In a semiconductor device and a method for manufacturing the same according to the present invention, for example, an insulating film is deposited on a silicon substrate, and a concave groove is formed in the insulating film in accordance with a predetermined wiring pattern. Titanium and palladium are deposited in sequence on the insulating film to form a titanium film and a palladium film, respectively. A silver film is formed on the palladium film by electroplating, and a groove-shaped silver wiring layer is formed by polishing. The resultant structure is annealed at a temperature of about 700.degree. C., and an intermetallic compound is formed by alloying the titanium film and palladium film with each other. Consequently, a burying type wiring layer whose resistance is lower than that of aluminum, is constituted by the silver wiring layer and intermetallic compound.
    Type: Grant
    Filed: May 25, 1994
    Date of Patent: March 19, 1996
    Assignees: Kabushiki Kaisha Toshiba, Ebara Corporation
    Inventors: Masahiro Miyata, Hirokazu Ezawa, Naoaki Ogure, Manabu Tsujimura, Takeyuki Ohdaira, Hiroaki Inoue, Yukio Ikeda
  • Patent number: 5480839
    Abstract: With a semiconductor device manufacturing method, a lower-layer interconnection is formed on a circuit board on which a plurality of semiconductor chips are mounted. Using a screen plate with openings corresponding to desired positions on the lower-layer interconnection, screen printing of a metal paste is effected, and the printed metal paste is dried and calcined by heat treatment to form a metal pillar on the lower-layer interconnection. An insulating film covering the lower-layer interconnection and the metal pillar is formed so that the tip of the metal pillar may be exposed. An upper-layer interconnection is formed on the insulating film so that this layer may contact with the exposed tip of the metal pillar.
    Type: Grant
    Filed: January 11, 1994
    Date of Patent: January 2, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hirokazu Ezawa, Masahiro Miyata