Patents by Inventor Masahiro Nishi

Masahiro Nishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11244133
    Abstract: This information processing apparatus includes an instruction determining unit and a signal output unit. The instruction determining unit determines an instruction related to communication using a code image with an external apparatus. The signal output unit outputs, on the basis of the determined instruction related to the communication, a signal for controlling an operation related to communication of the external apparatus. Accordingly, high usability can be provided for communication with the external apparatus.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: February 8, 2022
    Assignee: FELICA NETWORKS, INC.
    Inventor: Masahiro Nishi
  • Publication number: 20210271838
    Abstract: This information processing apparatus includes an instruction determining unit and a signal output unit. The instruction determining unit determines an instruction related to communication using a code image with an external apparatus. The signal output unit outputs, on the basis of the determined instruction related to the communication, a signal for controlling an operation related to communication of the external apparatus. Accordingly, high usability can be provided for communication with the external apparatus.
    Type: Application
    Filed: July 22, 2019
    Publication date: September 2, 2021
    Applicant: FeliCa Networks, Inc.
    Inventor: Masahiro NISHI
  • Patent number: 10740255
    Abstract: Provided is a control apparatus that can correctly obtain the execution status information of the instruction whose sender is the control apparatus itself. The controller (3) controls operations of the IO-Link device (2) via the IO-Link master (1), and includes the writing part (300) transmitting an instruction for the IO-Link device (2) and an identification of the instruction to the IO-Link master (1) and the reading part (301) retrieving an execution status information (status) indicating the execution status of the instruction by using the identification information.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: August 11, 2020
    Assignee: OMRON Corporation
    Inventors: Yasuhiro Kitamura, Atsushi Kamimura, Masahiro Nishi, Toshikatsu Nakamura
  • Patent number: 10446661
    Abstract: A semiconductor device includes a semiconductor layer formed on a substrate, an electrode contact window that includes a recess formed on a surface of the semiconductor layer, an inner wall having a slope, and a source electrode, a drain electrode, and a gate electrode formed on the semiconductor layer, in which the drain electrode is in contact with the slope of the inner wall.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: October 15, 2019
    Assignee: Sumitomo Electric Device Innovations, Inc.
    Inventor: Masahiro Nishi
  • Publication number: 20180277434
    Abstract: A process of forming an ohmic electrode containing aluminum (Al) on a nitride semiconductor material is disclosed. The process includes steps of: (a) depositing an ohmic metal on the semiconductor material; (b) forming an insulating film such that the insulating film covers a side of the ohmic metal but exposes a top of the ohmic metal; and (c) alloying the ohmic metal at a temperature higher than 500° C. for 30 to 60 seconds.
    Type: Application
    Filed: March 22, 2018
    Publication date: September 27, 2018
    Applicants: Sumitomo Electric Industries, Ltd., SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventors: Hiroyuki Ichikawa, Masahiro Nishi
  • Publication number: 20170300432
    Abstract: Provided is a control apparatus that can correctly obtain the execution status information of the instruction whose sender is the control apparatus itself. The controller (3) controls operations of the IO-Link device (2) via the IO-Link master (1), and includes the writing part (300) transmitting an instruction for the IO-Link device (2) and an identification of the instruction to the IO-Link master (1) and the reading part (301) retrieving an execution status information (status) indicating the execution status of the instruction by using the identification information.
    Type: Application
    Filed: April 13, 2017
    Publication date: October 19, 2017
    Applicant: OMRON Corporation
    Inventors: Yasuhiro KITAMURA, Atsushi KAMIMURA, Masahiro NISHI, Toshikatsu NAKAMURA
  • Publication number: 20170186851
    Abstract: A semiconductor device includes a semiconductor layer formed on a substrate, an electrode contact window that includes a recess formed on a surface of the semiconductor layer, an inner wall having a slope, and a source electrode, a drain electrode, and a gate electrode formed on the semiconductor layer, in which the drain electrode is in contact with the slope of the inner wall.
    Type: Application
    Filed: March 13, 2017
    Publication date: June 29, 2017
    Inventor: Masahiro Nishi
  • Patent number: 9640429
    Abstract: A method of fabricating a semiconductor device includes: forming a metal layer containing Al; forming an insulating film on the metal layer; forming an opening pattern to the insulating film, the metal layer being exposed in the opening pattern; and forming a wiring layer in the opening pattern, a first portion being disposed between an edge of the wiring layer and an edge of the opening pattern, a width of the first portion being 1 ?m or less, and the metal layer being exposed in the first portion.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: May 2, 2017
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Masahiro Nishi
  • Patent number: 9627506
    Abstract: A semiconductor device includes a semiconductor layer formed on a substrate, an electrode contact window that includes a recess formed on a surface of the semiconductor layer, an inner wall having a slope, and a source electrode, a drain electrode, and a gate electrode formed on the semiconductor layer, in which the drain electrode is in contact with the slope of the inner wall.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: April 18, 2017
    Assignee: Sumitomo Electric Device Innovations, Inc.
    Inventor: Masahiro Nishi
  • Patent number: 9564503
    Abstract: A manufacturing method according to an embodiment of this invention is a method of manufacturing a semiconductor device, which has: a first step of forming a first electrode 22 containing Ti or Ta on a top face of a nitride semiconductor layer 18; a second step of forming a second electrode 24 containing Al on a top face of the first electrode 22; a third step of forming a coating metal layer 26 covering at least one of an edge of a top face of the second electrode 24 and a side face of the second electrode 24, having a window 26a exposing the top face of the second electrode 24 in a region separated from the foregoing edge, and containing at least one of Ta, Mo, Pd, Ni, and Ti; and a step of performing a thermal treatment, after the third step.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: February 7, 2017
    Assignee: Sumitomo Electric Device Innovations, Inc.
    Inventor: Masahiro Nishi
  • Patent number: 9564504
    Abstract: A manufacturing method according to an embodiment of this invention is a method of manufacturing a semiconductor device, which has: a first step of forming a first electrode 22 containing Ti or Ta on a top face of a nitride semiconductor layer 18; a second step of forming a second electrode 24 containing Al on a top face of the first electrode 22; a third step of forming a coating metal layer 26 covering at least one of an edge of a top face of the second electrode 24 and a side face of the second electrode 24, having a window 26a exposing the top face of the second electrode 24 in a region separated from the foregoing edge, and containing at least one of Ta, Mo, Pd, Ni, and Ti; and a step of performing a thermal treatment, after the third step.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: February 7, 2017
    Assignee: Sumitomo Electric Device Innovations, Inc.
    Inventor: Masahiro Nishi
  • Patent number: 9484446
    Abstract: A semiconductor device includes: a nitride semiconductor layer; a first silicon nitride film that is formed on the nitride semiconductor layer, has a first opening whose inner wall is a forward tapered shape; a second silicon nitride film that is formed on the first silicon nitride film, and has a second opening whose inner wall is an inverse tapered shape; and a gate electrode formed so as to cover the whole surface of the nitride semiconductor layer exposed on the inside of the first opening; wherein a side wall of the gate electrode separates from the first silicon nitride film and the second silicon nitride film via a cavity.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: November 1, 2016
    Assignee: Sumitomo Electric Device Innovations, Inc.
    Inventor: Masahiro Nishi
  • Publication number: 20160260818
    Abstract: A semiconductor device includes a semiconductor layer formed on a substrate, an electrode contact window that includes a recess formed on a surface of the semiconductor layer, an inner wall having a slope, and a source electrode, a drain electrode, and a gate electrode formed on the semiconductor layer, in which the drain electrode is in contact with the slope of the inner wall.
    Type: Application
    Filed: March 18, 2016
    Publication date: September 8, 2016
    Inventor: Masahiro Nishi
  • Publication number: 20160225865
    Abstract: A manufacturing method according to an embodiment of this invention is a method of manufacturing a semiconductor device, which has: a first step of forming a first electrode 22 containing Ti or Ta on a top face of a nitride semiconductor layer 18; a second step of forming a second electrode 24 containing Al on a top face of the first electrode 22; a third step of forming a coating metal layer 26 covering at least one of an edge of a top face of the second electrode 24 and a side face of the second electrode 24, having a window 26a exposing the top face of the second electrode 24 in a region separated from the foregoing edge, and containing at least one of Ta, Mo, Pd, Ni, and Ti; and a step of performing a thermal treatment, after the third step.
    Type: Application
    Filed: February 3, 2016
    Publication date: August 4, 2016
    Inventor: Masahiro Nishi
  • Publication number: 20160225875
    Abstract: A manufacturing method according to an embodiment of this invention is a method of manufacturing a semiconductor device, which has: a first step of forming a first electrode 22 containing Ti or Ta on a top face of a nitride semiconductor layer 18; a second step of forming a second electrode 24 containing Al on a top face of the first electrode 22; a third step of forming a coating metal layer 26 covering at least one of an edge of a top face of the second electrode 24 and a side face of the second electrode 24, having a window 26a exposing the top face of the second electrode 24 in a region separated from the foregoing edge, and containing at least one of Ta, Mo, Pd, Ni, and Ti; and a step of performing a thermal treatment, after the third step.
    Type: Application
    Filed: February 3, 2016
    Publication date: August 4, 2016
    Inventor: Masahiro Nishi
  • Publication number: 20160172233
    Abstract: A method of fabricating a semiconductor device includes: forming a metal layer containing Al; forming an insulating film on the metal layer; forming an opening pattern to the insulating film, the metal layer being exposed in the opening pattern; and forming a wiring layer in the opening pattern, a first portion being disposed between an edge of the wiring layer and an edge of the opening pattern, a width of the first portion being 1 ?m or less, and the metal layer being exposed in the first portion.
    Type: Application
    Filed: February 25, 2016
    Publication date: June 16, 2016
    Inventor: Masahiro Nishi
  • Patent number: 9306030
    Abstract: A semiconductor device includes a semiconductor layer formed on a substrate, an electrode contact window that includes a recess formed on a surface of the semiconductor layer, an inner wall having a slope, and a source electrode, a drain electrode, and a gate electrode formed on the semiconductor layer, in which the drain electrode is in contact with the slope of the inner wall.
    Type: Grant
    Filed: April 10, 2014
    Date of Patent: April 5, 2016
    Assignee: Sumitomo Electric Device Innovations, Inc.
    Inventor: Masahiro Nishi
  • Patent number: 9305788
    Abstract: A method of fabricating a semiconductor device includes: forming a metal layer containing Al; forming an insulating film on the metal layer; forming an opening pattern to the insulating film, the metal layer being exposed in the opening pattern; and forming a wiring layer in the opening pattern, a first portion being disposed between an edge of the wiring layer and an edge of the opening pattern, a width of the first portion being 1 ?m or less, and the metal layer being exposed in the first portion.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: April 5, 2016
    Assignee: Sumitomo Electric Device Innovations, Inc.
    Inventor: Masahiro Nishi
  • Patent number: 9281370
    Abstract: A manufacturing method according to an embodiment of this invention is a method of manufacturing a semiconductor device, which has: a first step of forming a first electrode 22 containing Ti or Ta on a top face of a nitride semiconductor layer 18; a second step of forming a second electrode 24 containing Al on a top face of the first electrode 22; a third step of forming a coating metal layer 26 covering at least one of an edge of a top face of the second electrode 24 and a side face of the second electrode 24, having a window 26a exposing the top face of the second electrode 24 in a region separated from the foregoing edge, and containing at least one of Ta, Mo, Pd, Ni, and Ti; and a step of performing a thermal treatment, after the third step.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: March 8, 2016
    Assignee: Sumitomo Electric Device Innovations, Inc.
    Inventor: Masahiro Nishi
  • Publication number: 20150333138
    Abstract: A semiconductor device includes: a nitride semiconductor layer; a first silicon nitride film that is formed on the nitride semiconductor layer, has a first opening whose inner wall is a forward tapered shape; a second silicon nitride film that is formed on the first silicon nitride film, and has a second opening whose inner wall is an inverse tapered shape; and a gate electrode formed so as to cover the whole surface of the nitride semiconductor layer exposed on the inside of the first opening; wherein a side wall of the gate electrode separates from the first silicon nitride film and the second silicon nitride film via a cavity.
    Type: Application
    Filed: July 24, 2015
    Publication date: November 19, 2015
    Inventor: Masahiro Nishi