Patents by Inventor Masakazu Aoki

Masakazu Aoki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7026058
    Abstract: A multilayered hydrogen absorbing body is provided which is formed by laminating at least two types of hydrogen absorbing materials. The degrees of strains cause due to absorption/desorption of hydrogen are different between the hydrogen absorbing materials adjacent to each other.
    Type: Grant
    Filed: July 22, 2003
    Date of Patent: April 11, 2006
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Shin-ichi Towata, Masakazu Aoki, Tatsumi Hioki, Akio Itoh, Akihiko Koiwai, Toshihiro Mouri, Katsushi Saito
  • Patent number: 7005959
    Abstract: A vehicle key-less entry system includes a locking mechanism to lock or unlock vehicle doors; a door-handle detector to detect whether a door handle is manipulated and a manipulation mode when the door handle is detected as manipulated; a mobile device to record identification (ID) information and conduct non-contact communications using the ID information; an authenticator to perform an authentication procedure using the ID information through the non-contact communications with the mobile device when the door handle is detected as manipulated; and a locking controller to control the locking mechanism for locking or unlocking the vehicle door based on the manipulation mode detected by the door-handle detector when a result of the authentication procedure is positive. The door-handle detector may detect whether a door handle is manipulated only.
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: February 28, 2006
    Assignee: Fuji Jukogyo Kabushiki Kaisha
    Inventors: Yoshinori Amagasa, Noritoshi Yuzuriha, Nobuzi Suzuki, Masakazu Aoki
  • Patent number: 6991443
    Abstract: An oil injected screw compressor has an oil separating mechanism integrated with a compressor and hence is made compact in size. A male rotor and a female rotor are received in a rotor casing. The shafts of these rotors are arranged substantially in a horizontal direction. An inner cylindrical wall is arranged under the rotor casing with its center axis arranged substantially in a vertical direction and an outer wall is arranged substantially in a concentric position with the inner wall. A lower casing is hermetically joined to the outer wall. Oil in the working gas which is injected in the compression process of the oil injected screw compressor is primarily separated from the working gas between the inner wall and the outer wall. The primarily separated working gas flows up inside the inner wall and is guided through a manifold into an oil separating element case where the oil is secondarily separated from the working gas.
    Type: Grant
    Filed: February 11, 2004
    Date of Patent: January 31, 2006
    Assignee: Hitachi Industrial Equipment Systems Co., Ltd.
    Inventors: Masakazu Aoki, Masahiko Takano, Masaaki Toda
  • Patent number: 6970019
    Abstract: A semiconductor integrated circuit device is composed of logic gates each provided with MOS transistors. The semiconductor integrated circuit device includes a current control device. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors, that have both an operation mode and a low power back-up or sleep mode used for power reduction.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: November 29, 2005
    Inventors: Masashi Horiguchi, Kunio Uchiyama, Kiyoo Itoh, Takeshi Sakata, Masakazu Aoki, Takayuki Kawahara
  • Publication number: 20050219922
    Abstract: Method for manufacturing a memory device, the memory being a memory array with a spare bit line and being provided with a defect recovery scheme featuring a redundancy circuit. The redundancy circuit includes one or more comparing circuits having programmable elements which function as a memory for storing therein a defective address existing in the memory array. The programmable elements of the redundancy circuit can be programmed in accordance with any of a number of different types of defect modes. Each comparing circuit of the redundancy circuit compares information (data) inputted therein, for example, the column and row addresses which may be under the control of an address multiplex system, with that programmed in the programmable elements of the comparing circuit. On the basis of this comparison, an appropriate defect recovery is effected.
    Type: Application
    Filed: May 31, 2005
    Publication date: October 6, 2005
    Inventors: Masashi Horiguchi, Jun Etoh, Masakazu Aoki, Kiyoo Itoh
  • Publication number: 20050213414
    Abstract: A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.
    Type: Application
    Filed: May 18, 2005
    Publication date: September 29, 2005
    Inventors: Masashi Horiguchi, Kunio Uchiyama, Kiyoo Itoh, Takeshi Sakata, Masakazu Aoki, Takayuki Kawahara
  • Publication number: 20050152186
    Abstract: To reduce cost of defect redundancy and trimming in a semiconductor integrated circuit having multiple layer wirings and copper wirings, an address for salvaging a defect of a memory cell array in a semiconductor is stored by using a nonvolatile memory element constituting a floating electrode by a first layer of polysilicon, or the nonvolatile memory element is programmed in testing the semiconductor integrated circuit. As a result, a special process is not needed in forming the nonvolatile memory element. In other words, the nonvolatile memory element can be formed in a process of forming a CMOS device and an apparatus of a laser beam for programming is not needed since the programming is carried out in testing. Thus, the time necessary for programming can be shortened, and, therefore, testing costs can be reduced.
    Type: Application
    Filed: March 7, 2005
    Publication date: July 14, 2005
    Inventors: Koichiro Ishibashi, Shoji Shukuri, Kazumasa Yanagisawa, Junichi Nishimoto, Masanao Yamaoka, Masakazu Aoki
  • Publication number: 20050141114
    Abstract: In a vehicle door mirror device (10), an outer side surface (20B), with respect to a vehicle, of a projection (20) of a door mirror stay (16) is made to be flat. Further, an angle of the outer side surface (20B) with respect to a front-rear direction of the vehicle, inward or outward with respect to the vehicle, is not more than 2 degrees. Therefore, wind arriving at the outer side surface (20B) flows rearward with respect to the vehicle with fluctuation thereof being suppressed, and its flow is straightened. Furthermore, a radius of curvature of a corner portion (20E) at an outer rear side, with respect to the vehicle, of the projection (20) is not more than 15 mm. Therefore, wind arriving at the outer side surface (20B) of the projection (20) is suppressed from flowing along the corner portion (20E), and its flow is straightened. Thus, wind noise performance of the door mirror stay (16) can be improved.
    Type: Application
    Filed: March 19, 2003
    Publication date: June 30, 2005
    Applicant: Kabushiki Kaisha Tokai-Rika-Denki-Seisakusho
    Inventors: Toshinobu Mizutani, Masakazu Iwatsuki, Masakazu Aoki, Masaaki Itou, Yasunobu Okatsu
  • Patent number: 6909647
    Abstract: A semiconductor memory is provided with a defect recovery scheme featuring a redundancy circuit. The memory array in the memory has a plurality of word lines, a plurality of bit lines, a spare bit line, and a plurality of memory cells. The redundancy circuit includes one or more comparing circuits having programmable elements which function as a memory for storing therein a defective address existing in the memory array. The programmable elements of the redundancy circuit can be programmed in accordance with any of a number of different types of defect modes. Each comparing circuit of the redundancy circuit compares information (data) inputted therein, for example, the column and row addresses which may be under the control of an address multiplex system, with that programmed in the programmable elements of the comparing circuit. On the basis of this comparison, an appropriate defect recovery is effected.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: June 21, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Masashi Horiguchi, Jun Etoh, Masakazu Aoki, Kiyoo Itoh
  • Patent number: 6894944
    Abstract: To reduce cost of defect redundancy and trimming in a semiconductor integrated circuit having multiple layer wirings and copper wirings, an address for salvaging a defect of a memory cell array in a semiconductor is stored by using a nonvolatile memory element constituting a floating electrode by a first layer of polysilicon, or the nonvolatile memory element is programmed in testing the semiconductor integrated circuit. As a result, a special process is not needed in forming the nonvolatile memory element. In other words, the nonvolatile memory element can be formed in a process of forming a CMOS device and an apparatus of a laser beam for programming is not needed since the programming is carried out in testing. Thus, the time necessary for programming can be shortened, and, therefore, testing costs can be reduced.
    Type: Grant
    Filed: June 25, 2003
    Date of Patent: May 17, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Koichiro Ishibashi, Shoji Shukuri, Kazumasa Yanagisawa, Junichi Nishimoto, Masanao Yamaoka, Masakazu Aoki
  • Publication number: 20050023615
    Abstract: A field-effect semiconductor element implemented with a fewer number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature.
    Type: Application
    Filed: August 31, 2004
    Publication date: February 3, 2005
    Inventors: Kazuo Yano, Tomoyuki Ishii, Takashi Hashimoto, Koichi Seki, Masakazu Aoki, Takeshi Sakata, Yoshinobu Nakagome, Kan Takeuchi
  • Patent number: 6842597
    Abstract: A color image formation apparatus includes a plurality of stages of photosensitive drums provided for respective developing agents, the photosensitive drums arranged in a predetermined direction; and developer units which are provided for respective photosensitive drums and which develop electrostatic latent images formed on the photosensitive drums, wherein an overlap exists in the predetermined direction between a portion of each photosensitive drum and a portion of the developer unit provided so as to correspond to an adjacent photosensitive drum.
    Type: Grant
    Filed: February 28, 2003
    Date of Patent: January 11, 2005
    Assignee: Matsushita Electric Industrial Company, Inc.
    Inventors: Naoki Yamaguchi, Yuzo Kawano, Masakazu Aoki, Hirokazu Tasaka, Yoshihiro Mizoguchi
  • Patent number: 6833725
    Abstract: On a basic measurement unit arranged in a lattice shape on a chip, a resistance measurement circuit, a capacity measurement circuit, an n-type MOS transistor measurement circuit, a p-type MOS transistor measurement circuit, and a ring oscillator measurement circuit are mounted by several tens of patterns. Each measurement circuit mounted by several tens of patterns is connected to a measurement bus to constitute a measurement bus net in accordance with measured items. Switching of connection of the measurement bus net with a measurement terminal pad is electrically controlled properly by X, Y address selection signals outputted from X, Y address decoders to X, Y address selection signal lines.
    Type: Grant
    Filed: June 19, 2003
    Date of Patent: December 21, 2004
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Shin-ichi Ohkawa, Masakazu Aoki
  • Publication number: 20040253514
    Abstract: A hydrogen storage material is expressed by a composition formula, (Ca1-xAx)1-z(Si1-yBy)z, wherein “A” is at least one member selected from the group consisting of alkali metal elements, alkaline-earth metal elements, rare-earth elements, the elements of groups 3 through 6, Ni, Au, In, Tl, Sn, Fe, Co, Cu and Ag; “B” is at least one member selected from the group consisting of the elements of groups 7 through 17, rare-earth elements, Hf and Be; 0≦x<1 by atomic ratio; 0≦y<1 by atomic ratio; and 0.38≦z<0.58 by atomic ratio. It is lightweight as well as less expensive. In principle, neither high-temperature nor high-pressure activation is required, because it exhibits a high initial activity. The operation temperature can be lowered and the hydrogen absorption content can be enlarged by controlling the kind and substitution proportion of the substituent elements appropriately.
    Type: Application
    Filed: June 10, 2004
    Publication date: December 16, 2004
    Applicant: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO
    Inventors: Masakazu Aoki, Nobuko Oba, Shin-ichi Towata, Tatsuo Noritake
  • Publication number: 20040184329
    Abstract: A semiconductor memory is provided with a defect recovery scheme featuring a redundancy circuit. The memory array in the memory has a plurality of word lines, a plurality of bit lines, a spare bit line, and a plurality of memory cells. The redundancy circuit includes one or more comparing circuits having programmable elements which function as a memory for storing therein a defective address existing in the memory array. The programmable elements of the redundancy circuit can be programmed in accordance with any of a number of different types of defect modes. Each comparing circuit of the redundancy circuit compares information (data) inputted therein, for example, the column and row addresses which may be under the control of an address multiplex system, with that programmed in the programmable elements of the comparing circuit. On the basis of this comparison, an appropriate defect recovery is effected.
    Type: Application
    Filed: March 31, 2004
    Publication date: September 23, 2004
    Inventors: Masashi Horiguchi, Jun Etoh, Masakazu Aoki, Kiyoo Itoh
  • Publication number: 20040184941
    Abstract: An oil injected screw compressor has an oil separating mechanism integrated with a compressor and hence is made compact in size. A male rotor and a female rotor are received in a rotor casing. The shafts of these rotors are arranged substantially in a horizontal direction. An inner cylindrical wall is arranged under the rotor casing with its center axis arranged substantially in a vertical direction and an outer wall is arranged substantially in a concentric position with the inner wall. A lower casing is hermetically joined to the outer wall. Oil in the working gas which is injected in the compression process of the oil injected screw compressor is primarily separated from the working gas between the inner wall and the outer wall. The primarily separated working gas flows up inside the inner wall and is guided through a manifold into an oil separating element case where the oil is secondarily separated from the working gas.
    Type: Application
    Filed: February 11, 2004
    Publication date: September 23, 2004
    Inventors: Masakazu Aoki, Masahiko Takano, Masaaki Toda
  • Patent number: 6787841
    Abstract: A field-effect semiconductor element implemented with a fewer number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: September 7, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Kazuo Yano, Tomoyuki Ishii, Takashi Hashimoto, Koichi Seki, Masakazu Aoki, Takeshi Sakata, Yoshinobu Nakagome, Kan Takeuchi
  • Patent number: 6754114
    Abstract: A semiconductor memory is provided with a defect recovery scheme featuring a redundancy circuit. The memory array in the memory has a plurality of word lines, a plurality of bit lines, a spare bit line, and a plurality of memory cells. The redundancy circuit includes one or more comparing circuits having programmable elements which function as a memory for storing therein a defective address existing in the memory array. The programmable elements of the redundancy circuit can be programmed in accordance with any of a number of different types of defect modes. Each comparing circuit of the redundancy circuit compares information (data) inputted therein, for example, the column and row addresses which may be under the control of an address multiplex system, with that programmed in the programmable elements of the comparing circuit. On the basis of this comparison, an appropriate defect recovery is effected.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: June 22, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Masashi Horiguchi, Jun Etoh, Masakazu Aoki, Kiyoo Itoh
  • Publication number: 20040110023
    Abstract: A multilayered hydrogen absorbing body is provided which is formed by laminating at least two types of hydrogen absorbing materials. The degrees of strains cause due to absorption/desorption of hydrogen are different between the hydrogen absorbing materials adjacent to each other.
    Type: Application
    Filed: July 22, 2003
    Publication date: June 10, 2004
    Applicant: Toyota Jidosha Kabushiki Kaisha
    Inventors: Shin-Ichi Towata, Masakazu Aoki, Tatsumi Hioki, Akio Itoh, Akihiko Koiwai, Toshihiro Mouri, Katsushi Saito
  • Patent number: 6746140
    Abstract: A rear-view mirror for a vehicle. The rear-view mirror has a mirrow body at which is formed an accommodating member. A lamp house containing a lamp bulb and a secondary battery is accommodated in the accommodating member by holders for holding the lamp house from below. The lamp house is pulled out from the accommodating member to illuminate a desired position.
    Type: Grant
    Filed: October 2, 2001
    Date of Patent: June 8, 2004
    Assignee: Kabushiki Kaisha Tokai-Rika-Denki-Seisakusho
    Inventors: Takashi Ichikawa, Masakazu Aoki, Tadashi Ejiri, Masami Hosono, Hiroyuki Kato, Kenichi Jinushi